mcu8951.tan.qmsg

KX_DVP3F型FPGA应用板/开发板（全套）包括： &#61592 CycloneII系列FPGA EP2C8Q208C8 40万们

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "K1P97 register register CNT4B:inst\|Q1\[0\] CNT4B:inst\|Q1\[3\] 360.1 MHz Internal " "Info: Clock \"K1P97\" Internal fmax is restricted to 360.1 MHz between source register \"CNT4B:inst\|Q1\[0\]\" and destination register \"CNT4B:inst\|Q1\[3\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.808 ns + Longest register register " "Info: + Longest register to register delay is 1.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CNT4B:inst\|Q1\[0\] 1 REG LCFF_X29_Y2_N13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y2_N13; Fanout = 5; REG Node = 'CNT4B:inst\|Q1\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT4B:inst|Q1[0] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.650 ns) 1.141 ns CNT4B:inst\|Q1\[3\]~48 2 COMB LCCOMB_X29_Y2_N30 1 " "Info: 2: + IC(0.491 ns) + CELL(0.650 ns) = 1.141 ns; Loc. = LCCOMB_X29_Y2_N30; Fanout = 1; COMB Node = 'CNT4B:inst\|Q1\[3\]~48'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.141 ns" { CNT4B:inst|Q1[0] CNT4B:inst|Q1[3]~48 } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.353 ns) + CELL(0.206 ns) 1.700 ns CNT4B:inst\|Q1\[3\]~feeder 3 COMB LCCOMB_X29_Y2_N18 1 " "Info: 3: + IC(0.353 ns) + CELL(0.206 ns) = 1.700 ns; Loc. = LCCOMB_X29_Y2_N18; Fanout = 1; COMB Node = 'CNT4B:inst\|Q1\[3\]~feeder'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.559 ns" { CNT4B:inst|Q1[3]~48 CNT4B:inst|Q1[3]~feeder } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.808 ns CNT4B:inst\|Q1\[3\] 4 REG LCFF_X29_Y2_N19 2 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 1.808 ns; Loc. = LCFF_X29_Y2_N19; Fanout = 2; REG Node = 'CNT4B:inst\|Q1\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { CNT4B:inst|Q1[3]~feeder CNT4B:inst|Q1[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.964 ns ( 53.32 % ) " "Info: Total cell delay = 0.964 ns ( 53.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.844 ns ( 46.68 % ) " "Info: Total interconnect delay = 0.844 ns ( 46.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { CNT4B:inst|Q1[0] CNT4B:inst|Q1[3]~48 CNT4B:inst|Q1[3]~feeder CNT4B:inst|Q1[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.808 ns" { CNT4B:inst|Q1[0] CNT4B:inst|Q1[3]~48 CNT4B:inst|Q1[3]~feeder CNT4B:inst|Q1[3] } { 0.000ns 0.491ns 0.353ns 0.000ns } { 0.000ns 0.650ns 0.206ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "K1P97 destination 2.980 ns + Shortest register " "Info: + Shortest clock path from clock \"K1P97\" to destination register is 2.980 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns K1P97 1 CLK PIN_97 4 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 4; CLK Node = 'K1P97'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { K1P97 } "NODE_NAME" } } { "MCU8951.bdf" "" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -536 232 440 -520 "K1P97" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.666 ns) 2.980 ns CNT4B:inst\|Q1\[3\] 2 REG LCFF_X29_Y2_N19 2 " "Info: 2: + IC(1.320 ns) + CELL(0.666 ns) = 2.980 ns; Loc. = LCFF_X29_Y2_N19; Fanout = 2; REG Node = 'CNT4B:inst\|Q1\[3\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.986 ns" { K1P97 CNT4B:inst|Q1[3] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 55.70 % ) " "Info: Total cell delay = 1.660 ns ( 55.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.320 ns ( 44.30 % ) " "Info: Total interconnect delay = 1.320 ns ( 44.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.980 ns" { K1P97 CNT4B:inst|Q1[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.980 ns" { K1P97 K1P97~combout CNT4B:inst|Q1[3] } { 0.000ns 0.000ns 1.320ns } { 0.000ns 0.994ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "K1P97 source 2.980 ns - Longest register " "Info: - Longest clock path from clock \"K1P97\" to source register is 2.980 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns K1P97 1 CLK PIN_97 4 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 4; CLK Node = 'K1P97'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { K1P97 } "NODE_NAME" } } { "MCU8951.bdf" "" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -536 232 440 -520 "K1P97" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.666 ns) 2.980 ns CNT4B:inst\|Q1\[0\] 2 REG LCFF_X29_Y2_N13 5 " "Info: 2: + IC(1.320 ns) + CELL(0.666 ns) = 2.980 ns; Loc. = LCFF_X29_Y2_N13; Fanout = 5; REG Node = 'CNT4B:inst\|Q1\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.986 ns" { K1P97 CNT4B:inst|Q1[0] } "NODE_NAME" } } { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.660 ns ( 55.70 % ) " "Info: Total cell delay = 1.660 ns ( 55.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.320 ns ( 44.30 % ) " "Info: Total interconnect delay = 1.320 ns ( 44.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.980 ns" { K1P97 CNT4B:inst|Q1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.980 ns" { K1P97 K1P97~combout CNT4B:inst|Q1[0] } { 0.000ns 0.000ns 1.320ns } { 0.000ns 0.994ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.980 ns" { K1P97 CNT4B:inst|Q1[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.980 ns" { K1P97 K1P97~combout CNT4B:inst|Q1[3] } { 0.000ns 0.000ns 1.320ns } { 0.000ns 0.994ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.980 ns" { K1P97 CNT4B:inst|Q1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.980 ns" { K1P97 K1P97~combout CNT4B:inst|Q1[0] } { 0.000ns 0.000ns 1.320ns } { 0.000ns 0.994ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.808 ns" { CNT4B:inst|Q1[0] CNT4B:inst|Q1[3]~48 CNT4B:inst|Q1[3]~feeder CNT4B:inst|Q1[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.808 ns" { CNT4B:inst|Q1[0] CNT4B:inst|Q1[3]~48 CNT4B:inst|Q1[3]~feeder CNT4B:inst|Q1[3] } { 0.000ns 0.491ns 0.353ns 0.000ns } { 0.000ns 0.650ns 0.206ns 0.108ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.980 ns" { K1P97 CNT4B:inst|Q1[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.980 ns" { K1P97 K1P97~combout CNT4B:inst|Q1[3] } { 0.000ns 0.000ns 1.320ns } { 0.000ns 0.994ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.980 ns" { K1P97 CNT4B:inst|Q1[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.980 ns" { K1P97 K1P97~combout CNT4B:inst|Q1[0] } { 0.000ns 0.000ns 1.320ns } { 0.000ns 0.994ns 0.666ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CNT4B:inst|Q1[3] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { CNT4B:inst|Q1[3] } {  } {  } } } { "CNT4B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/CNT4B.vhd" 14 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll2:inst13\|altpll:altpll_component\|_clk0 register REG32B:inst12\|DOUT\[2\] register REG32B:inst12\|DOUT\[2\] 499 ps " "Info: Minimum slack time is 499 ps for clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" between source register \"REG32B:inst12\|DOUT\[2\]\" and destination register \"REG32B:inst12\|DOUT\[2\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.501 ns + Shortest register register " "Info: + Shortest register to register delay is 0.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG32B:inst12\|DOUT\[2\] 1 REG LCFF_X1_Y9_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N3; Fanout = 3; REG Node = 'REG32B:inst12\|DOUT\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.393 ns) 0.393 ns REG32B:inst12\|DOUT\[2\]~178 2 COMB LCCOMB_X1_Y9_N2 1 " "Info: 2: + IC(0.000 ns) + CELL(0.393 ns) = 0.393 ns; Loc. = LCCOMB_X1_Y9_N2; Fanout = 1; COMB Node = 'REG32B:inst12\|DOUT\[2\]~178'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.393 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[2]~178 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.501 ns REG32B:inst12\|DOUT\[2\] 3 REG LCFF_X1_Y9_N3 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.501 ns; Loc. = LCFF_X1_Y9_N3; Fanout = 3; REG Node = 'REG32B:inst12\|DOUT\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { REG32B:inst12|DOUT[2]~178 REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.501 ns ( 100.00 % ) " "Info: Total cell delay = 0.501 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.501 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[2]~178 REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "0.501 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[2]~178 REG32B:inst12|DOUT[2] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.393ns 0.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.002 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.002 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.388 ns " "Info: + Latch edge is -2.388 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll2:inst13\|altpll:altpll_component\|_clk0 33.333 ns -2.388 ns  50 " "Info: Clock period of Destination clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" is 33.333 ns with  offset of -2.388 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.388 ns " "Info: - Launch edge is -2.388 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll2:inst13\|altpll:altpll_component\|_clk0 33.333 ns -2.388 ns  50 " "Info: Clock period of Source clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" is 33.333 ns with  offset of -2.388 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll2:inst13\|altpll:altpll_component\|_clk0 destination 2.453 ns + Longest register " "Info: + Longest clock path from clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" to destination register is 2.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll2:inst13\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll2:inst13\|altpll:altpll_component\|_clk0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll2:inst13|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.916 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.453 ns REG32B:inst12\|DOUT\[2\] 3 REG LCFF_X1_Y9_N3 3 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.453 ns; Loc. = LCFF_X1_Y9_N3; Fanout = 3; REG Node = 'REG32B:inst12\|DOUT\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 27.15 % ) " "Info: Total cell delay = 0.666 ns ( 27.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.787 ns ( 72.85 % ) " "Info: Total interconnect delay = 1.787 ns ( 72.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } { 0.000ns 0.916ns 0.871ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll2:inst13\|altpll:altpll_component\|_clk0 source 2.453 ns - Shortest register " "Info: - Shortest clock path from clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" to source register is 2.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll2:inst13\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll2:inst13\|altpll:altpll_component\|_clk0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll2:inst13|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.916 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.453 ns REG32B:inst12\|DOUT\[2\] 3 REG LCFF_X1_Y9_N3 3 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.453 ns; Loc. = LCFF_X1_Y9_N3; Fanout = 3; REG Node = 'REG32B:inst12\|DOUT\[2\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 27.15 % ) " "Info: Total cell delay = 0.666 ns ( 27.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.787 ns ( 72.85 % ) " "Info: Total interconnect delay = 1.787 ns ( 72.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld