📄 mcu8951.tan.qmsg
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{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll2:inst13\|altpll:altpll_component\|_clk0 register REG32B:inst12\|DOUT\[2\] register REG32B:inst12\|DOUT\[31\] 28.482 ns " "Info: Slack time is 28.482 ns for clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" between source register \"REG32B:inst12\|DOUT\[2\]\" and destination register \"REG32B:inst12\|DOUT\[31\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "206.14 MHz 4.851 ns " "Info: Fmax is 206.14 MHz (period= 4.851 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "33.088 ns + Largest register register " "Info: + Largest register to register requirement is 33.088 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "33.333 ns + " "Info: + Setup relationship between source and destination is 33.333 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 30.945 ns " "Info: + Latch edge is 30.945 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll2:inst13\|altpll:altpll_component\|_clk0 33.333 ns -2.388 ns 50 " "Info: Clock period of Destination clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" is 33.333 ns with offset of -2.388 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.388 ns " "Info: - Launch edge is -2.388 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll2:inst13\|altpll:altpll_component\|_clk0 33.333 ns -2.388 ns 50 " "Info: Clock period of Source clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" is 33.333 ns with offset of -2.388 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.019 ns + Largest " "Info: + Largest clock skew is 0.019 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll2:inst13\|altpll:altpll_component\|_clk0 destination 2.472 ns + Shortest register " "Info: + Shortest clock path from clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" to destination register is 2.472 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll2:inst13\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll2:inst13\|altpll:altpll_component\|_clk0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll2:inst13|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.916 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.890 ns) + CELL(0.666 ns) 2.472 ns REG32B:inst12\|DOUT\[31\] 3 REG LCFF_X1_Y8_N29 2 " "Info: 3: + IC(0.890 ns) + CELL(0.666 ns) = 2.472 ns; Loc. = LCFF_X1_Y8_N29; Fanout = 2; REG Node = 'REG32B:inst12\|DOUT\[31\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.556 ns" { pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.94 % ) " "Info: Total cell delay = 0.666 ns ( 26.94 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.806 ns ( 73.06 % ) " "Info: Total interconnect delay = 1.806 ns ( 73.06 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } { 0.000ns 0.916ns 0.890ns } { 0.000ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll2:inst13\|altpll:altpll_component\|_clk0 source 2.453 ns - Longest register " "Info: - Longest clock path from clock \"pll2:inst13\|altpll:altpll_component\|_clk0\" to source register is 2.453 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll2:inst13\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll2:inst13\|altpll:altpll_component\|_clk0'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll2:inst13|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'pll2:inst13\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.916 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.666 ns) 2.453 ns REG32B:inst12\|DOUT\[2\] 3 REG LCFF_X1_Y9_N3 3 " "Info: 3: + IC(0.871 ns) + CELL(0.666 ns) = 2.453 ns; Loc. = LCFF_X1_Y9_N3; Fanout = 3; REG Node = 'REG32B:inst12\|DOUT\[2\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.537 ns" { pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 27.15 % ) " "Info: Total cell delay = 0.666 ns ( 27.15 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.787 ns ( 72.85 % ) " "Info: Total interconnect delay = 1.787 ns ( 72.85 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } { 0.000ns 0.916ns 0.871ns } { 0.000ns 0.000ns 0.666ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } { 0.000ns 0.916ns 0.890ns } { 0.000ns 0.000ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } { 0.000ns 0.916ns 0.871ns } { 0.000ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" { } { { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" { } { { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } { 0.000ns 0.916ns 0.890ns } { 0.000ns 0.000ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } { 0.000ns 0.916ns 0.871ns } { 0.000ns 0.000ns 0.666ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.606 ns - Longest register register " "Info: - Longest register to register delay is 4.606 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns REG32B:inst12\|DOUT\[2\] 1 REG LCFF_X1_Y9_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y9_N3; Fanout = 3; REG Node = 'REG32B:inst12\|DOUT\[2\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.621 ns) 1.373 ns REG32B:inst12\|DOUT\[3\]~149 2 COMB LCCOMB_X1_Y9_N4 2 " "Info: 2: + IC(0.752 ns) + CELL(0.621 ns) = 1.373 ns; Loc. = LCCOMB_X1_Y9_N4; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[3\]~149'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.373 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[3]~149 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.459 ns REG32B:inst12\|DOUT\[4\]~150 3 COMB LCCOMB_X1_Y9_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.459 ns; Loc. = LCCOMB_X1_Y9_N6; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[4\]~150'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[3]~149 REG32B:inst12|DOUT[4]~150 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.545 ns REG32B:inst12\|DOUT\[5\]~151 4 COMB LCCOMB_X1_Y9_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.545 ns; Loc. = LCCOMB_X1_Y9_N8; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[5\]~151'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[4]~150 REG32B:inst12|DOUT[5]~151 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.631 ns REG32B:inst12\|DOUT\[6\]~152 5 COMB LCCOMB_X1_Y9_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.631 ns; Loc. = LCCOMB_X1_Y9_N10; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[6\]~152'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[5]~151 REG32B:inst12|DOUT[6]~152 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.717 ns REG32B:inst12\|DOUT\[7\]~153 6 COMB LCCOMB_X1_Y9_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.086 ns) = 1.717 ns; Loc. = LCCOMB_X1_Y9_N12; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[7\]~153'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[6]~152 REG32B:inst12|DOUT[7]~153 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.907 ns REG32B:inst12\|DOUT\[8\]~154 7 COMB LCCOMB_X1_Y9_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.190 ns) = 1.907 ns; Loc. = LCCOMB_X1_Y9_N14; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[8\]~154'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { REG32B:inst12|DOUT[7]~153 REG32B:inst12|DOUT[8]~154 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.993 ns REG32B:inst12\|DOUT\[9\]~155 8 COMB LCCOMB_X1_Y9_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.993 ns; Loc. = LCCOMB_X1_Y9_N16; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[9\]~155'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[8]~154 REG32B:inst12|DOUT[9]~155 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.079 ns REG32B:inst12\|DOUT\[10\]~156 9 COMB LCCOMB_X1_Y9_N18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 2.079 ns; Loc. = LCCOMB_X1_Y9_N18; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[10\]~156'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[9]~155 REG32B:inst12|DOUT[10]~156 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.165 ns REG32B:inst12\|DOUT\[11\]~157 10 COMB LCCOMB_X1_Y9_N20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 2.165 ns; Loc. = LCCOMB_X1_Y9_N20; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[11\]~157'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[10]~156 REG32B:inst12|DOUT[11]~157 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.251 ns REG32B:inst12\|DOUT\[12\]~158 11 COMB LCCOMB_X1_Y9_N22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 2.251 ns; Loc. = LCCOMB_X1_Y9_N22; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[12\]~158'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[11]~157 REG32B:inst12|DOUT[12]~158 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.337 ns REG32B:inst12\|DOUT\[13\]~159 12 COMB LCCOMB_X1_Y9_N24 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.337 ns; Loc. = LCCOMB_X1_Y9_N24; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[13\]~159'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[12]~158 REG32B:inst12|DOUT[13]~159 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.423 ns REG32B:inst12\|DOUT\[14\]~160 13 COMB LCCOMB_X1_Y9_N26 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.423 ns; Loc. = LCCOMB_X1_Y9_N26; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[14\]~160'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[13]~159 REG32B:inst12|DOUT[14]~160 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.509 ns REG32B:inst12\|DOUT\[15\]~161 14 COMB LCCOMB_X1_Y9_N28 2 " "Info: 14: + IC(0.000 ns) + CELL(0.086 ns) = 2.509 ns; Loc. = LCCOMB_X1_Y9_N28; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[15\]~161'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[14]~160 REG32B:inst12|DOUT[15]~161 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.684 ns REG32B:inst12\|DOUT\[16\]~162 15 COMB LCCOMB_X1_Y9_N30 2 " "Info: 15: + IC(0.000 ns) + CELL(0.175 ns) = 2.684 ns; Loc. = LCCOMB_X1_Y9_N30; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[16\]~162'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.175 ns" { REG32B:inst12|DOUT[15]~161 REG32B:inst12|DOUT[16]~162 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.770 ns REG32B:inst12\|DOUT\[17\]~163 16 COMB LCCOMB_X1_Y8_N0 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.770 ns; Loc. = LCCOMB_X1_Y8_N0; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[17\]~163'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[16]~162 REG32B:inst12|DOUT[17]~163 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.856 ns REG32B:inst12\|DOUT\[18\]~164 17 COMB LCCOMB_X1_Y8_N2 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.856 ns; Loc. = LCCOMB_X1_Y8_N2; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[18\]~164'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[17]~163 REG32B:inst12|DOUT[18]~164 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.942 ns REG32B:inst12\|DOUT\[19\]~165 18 COMB LCCOMB_X1_Y8_N4 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.942 ns; Loc. = LCCOMB_X1_Y8_N4; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[19\]~165'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[18]~164 REG32B:inst12|DOUT[19]~165 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.028 ns REG32B:inst12\|DOUT\[20\]~166 19 COMB LCCOMB_X1_Y8_N6 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 3.028 ns; Loc. = LCCOMB_X1_Y8_N6; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[20\]~166'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[19]~165 REG32B:inst12|DOUT[20]~166 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.114 ns REG32B:inst12\|DOUT\[21\]~167 20 COMB LCCOMB_X1_Y8_N8 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 3.114 ns; Loc. = LCCOMB_X1_Y8_N8; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[21\]~167'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[20]~166 REG32B:inst12|DOUT[21]~167 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.200 ns REG32B:inst12\|DOUT\[22\]~168 21 COMB LCCOMB_X1_Y8_N10 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 3.200 ns; Loc. = LCCOMB_X1_Y8_N10; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[22\]~168'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[21]~167 REG32B:inst12|DOUT[22]~168 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.286 ns REG32B:inst12\|DOUT\[23\]~169 22 COMB LCCOMB_X1_Y8_N12 2 " "Info: 22: + IC(0.000 ns) + CELL(0.086 ns) = 3.286 ns; Loc. = LCCOMB_X1_Y8_N12; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[23\]~169'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[22]~168 REG32B:inst12|DOUT[23]~169 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.476 ns REG32B:inst12\|DOUT\[24\]~170 23 COMB LCCOMB_X1_Y8_N14 2 " "Info: 23: + IC(0.000 ns) + CELL(0.190 ns) = 3.476 ns; Loc. = LCCOMB_X1_Y8_N14; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[24\]~170'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.190 ns" { REG32B:inst12|DOUT[23]~169 REG32B:inst12|DOUT[24]~170 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.562 ns REG32B:inst12\|DOUT\[25\]~171 24 COMB LCCOMB_X1_Y8_N16 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.562 ns; Loc. = LCCOMB_X1_Y8_N16; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[25\]~171'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[24]~170 REG32B:inst12|DOUT[25]~171 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.648 ns REG32B:inst12\|DOUT\[26\]~172 25 COMB LCCOMB_X1_Y8_N18 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.648 ns; Loc. = LCCOMB_X1_Y8_N18; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[26\]~172'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[25]~171 REG32B:inst12|DOUT[26]~172 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.734 ns REG32B:inst12\|DOUT\[27\]~173 26 COMB LCCOMB_X1_Y8_N20 2 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.734 ns; Loc. = LCCOMB_X1_Y8_N20; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[27\]~173'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[26]~172 REG32B:inst12|DOUT[27]~173 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.820 ns REG32B:inst12\|DOUT\[28\]~174 27 COMB LCCOMB_X1_Y8_N22 2 " "Info: 27: + IC(0.000 ns) + CELL(0.086 ns) = 3.820 ns; Loc. = LCCOMB_X1_Y8_N22; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[28\]~174'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[27]~173 REG32B:inst12|DOUT[28]~174 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.906 ns REG32B:inst12\|DOUT\[29\]~175 28 COMB LCCOMB_X1_Y8_N24 2 " "Info: 28: + IC(0.000 ns) + CELL(0.086 ns) = 3.906 ns; Loc. = LCCOMB_X1_Y8_N24; Fanout = 2; COMB Node = 'REG32B:inst12\|DOUT\[29\]~175'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[28]~174 REG32B:inst12|DOUT[29]~175 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.992 ns REG32B:inst12\|DOUT\[30\]~176 29 COMB LCCOMB_X1_Y8_N26 1 " "Info: 29: + IC(0.000 ns) + CELL(0.086 ns) = 3.992 ns; Loc. = LCCOMB_X1_Y8_N26; Fanout = 1; COMB Node = 'REG32B:inst12\|DOUT\[30\]~176'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.086 ns" { REG32B:inst12|DOUT[29]~175 REG32B:inst12|DOUT[30]~176 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 4.498 ns REG32B:inst12\|DOUT\[31\]~120 30 COMB LCCOMB_X1_Y8_N28 1 " "Info: 30: + IC(0.000 ns) + CELL(0.506 ns) = 4.498 ns; Loc. = LCCOMB_X1_Y8_N28; Fanout = 1; COMB Node = 'REG32B:inst12\|DOUT\[31\]~120'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.506 ns" { REG32B:inst12|DOUT[30]~176 REG32B:inst12|DOUT[31]~120 } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.606 ns REG32B:inst12\|DOUT\[31\] 31 REG LCFF_X1_Y8_N29 2 " "Info: 31: + IC(0.000 ns) + CELL(0.108 ns) = 4.606 ns; Loc. = LCFF_X1_Y8_N29; Fanout = 2; REG Node = 'REG32B:inst12\|DOUT\[31\]'" { } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.108 ns" { REG32B:inst12|DOUT[31]~120 REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.854 ns ( 83.67 % ) " "Info: Total cell delay = 3.854 ns ( 83.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.752 ns ( 16.33 % ) " "Info: Total interconnect delay = 0.752 ns ( 16.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.606 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[3]~149 REG32B:inst12|DOUT[4]~150 REG32B:inst12|DOUT[5]~151 REG32B:inst12|DOUT[6]~152 REG32B:inst12|DOUT[7]~153 REG32B:inst12|DOUT[8]~154 REG32B:inst12|DOUT[9]~155 REG32B:inst12|DOUT[10]~156 REG32B:inst12|DOUT[11]~157 REG32B:inst12|DOUT[12]~158 REG32B:inst12|DOUT[13]~159 REG32B:inst12|DOUT[14]~160 REG32B:inst12|DOUT[15]~161 REG32B:inst12|DOUT[16]~162 REG32B:inst12|DOUT[17]~163 REG32B:inst12|DOUT[18]~164 REG32B:inst12|DOUT[19]~165 REG32B:inst12|DOUT[20]~166 REG32B:inst12|DOUT[21]~167 REG32B:inst12|DOUT[22]~168 REG32B:inst12|DOUT[23]~169 REG32B:inst12|DOUT[24]~170 REG32B:inst12|DOUT[25]~171 REG32B:inst12|DOUT[26]~172 REG32B:inst12|DOUT[27]~173 REG32B:inst12|DOUT[28]~174 REG32B:inst12|DOUT[29]~175 REG32B:inst12|DOUT[30]~176 REG32B:inst12|DOUT[31]~120 REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.606 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[3]~149 REG32B:inst12|DOUT[4]~150 REG32B:inst12|DOUT[5]~151 REG32B:inst12|DOUT[6]~152 REG32B:inst12|DOUT[7]~153 REG32B:inst12|DOUT[8]~154 REG32B:inst12|DOUT[9]~155 REG32B:inst12|DOUT[10]~156 REG32B:inst12|DOUT[11]~157 REG32B:inst12|DOUT[12]~158 REG32B:inst12|DOUT[13]~159 REG32B:inst12|DOUT[14]~160 REG32B:inst12|DOUT[15]~161 REG32B:inst12|DOUT[16]~162 REG32B:inst12|DOUT[17]~163 REG32B:inst12|DOUT[18]~164 REG32B:inst12|DOUT[19]~165 REG32B:inst12|DOUT[20]~166 REG32B:inst12|DOUT[21]~167 REG32B:inst12|DOUT[22]~168 REG32B:inst12|DOUT[23]~169 REG32B:inst12|DOUT[24]~170 REG32B:inst12|DOUT[25]~171 REG32B:inst12|DOUT[26]~172 REG32B:inst12|DOUT[27]~173 REG32B:inst12|DOUT[28]~174 REG32B:inst12|DOUT[29]~175 REG32B:inst12|DOUT[30]~176 REG32B:inst12|DOUT[31]~120 REG32B:inst12|DOUT[31] } { 0.000ns 0.752ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.472 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[31] } { 0.000ns 0.916ns 0.890ns } { 0.000ns 0.000ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.453 ns" { pll2:inst13|altpll:altpll_component|_clk0 pll2:inst13|altpll:altpll_component|_clk0~clkctrl REG32B:inst12|DOUT[2] } { 0.000ns 0.916ns 0.871ns } { 0.000ns 0.000ns 0.666ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.606 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[3]~149 REG32B:inst12|DOUT[4]~150 REG32B:inst12|DOUT[5]~151 REG32B:inst12|DOUT[6]~152 REG32B:inst12|DOUT[7]~153 REG32B:inst12|DOUT[8]~154 REG32B:inst12|DOUT[9]~155 REG32B:inst12|DOUT[10]~156 REG32B:inst12|DOUT[11]~157 REG32B:inst12|DOUT[12]~158 REG32B:inst12|DOUT[13]~159 REG32B:inst12|DOUT[14]~160 REG32B:inst12|DOUT[15]~161 REG32B:inst12|DOUT[16]~162 REG32B:inst12|DOUT[17]~163 REG32B:inst12|DOUT[18]~164 REG32B:inst12|DOUT[19]~165 REG32B:inst12|DOUT[20]~166 REG32B:inst12|DOUT[21]~167 REG32B:inst12|DOUT[22]~168 REG32B:inst12|DOUT[23]~169 REG32B:inst12|DOUT[24]~170 REG32B:inst12|DOUT[25]~171 REG32B:inst12|DOUT[26]~172 REG32B:inst12|DOUT[27]~173 REG32B:inst12|DOUT[28]~174 REG32B:inst12|DOUT[29]~175 REG32B:inst12|DOUT[30]~176 REG32B:inst12|DOUT[31]~120 REG32B:inst12|DOUT[31] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "4.606 ns" { REG32B:inst12|DOUT[2] REG32B:inst12|DOUT[3]~149 REG32B:inst12|DOUT[4]~150 REG32B:inst12|DOUT[5]~151 REG32B:inst12|DOUT[6]~152 REG32B:inst12|DOUT[7]~153 REG32B:inst12|DOUT[8]~154 REG32B:inst12|DOUT[9]~155 REG32B:inst12|DOUT[10]~156 REG32B:inst12|DOUT[11]~157 REG32B:inst12|DOUT[12]~158 REG32B:inst12|DOUT[13]~159 REG32B:inst12|DOUT[14]~160 REG32B:inst12|DOUT[15]~161 REG32B:inst12|DOUT[16]~162 REG32B:inst12|DOUT[17]~163 REG32B:inst12|DOUT[18]~164 REG32B:inst12|DOUT[19]~165 REG32B:inst12|DOUT[20]~166 REG32B:inst12|DOUT[21]~167 REG32B:inst12|DOUT[22]~168 REG32B:inst12|DOUT[23]~169 REG32B:inst12|DOUT[24]~170 REG32B:inst12|DOUT[25]~171 REG32B:inst12|DOUT[26]~172 REG32B:inst12|DOUT[27]~173 REG32B:inst12|DOUT[28]~174 REG32B:inst12|DOUT[29]~175 REG32B:inst12|DOUT[30]~176 REG32B:inst12|DOUT[31]~120 REG32B:inst12|DOUT[31] } { 0.000ns 0.752ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.108ns } } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
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