mcu8951.tan.qmsg

KX_DVP3F型FPGA应用板/开发板（全套）包括： &#61592 CycloneII系列FPGA EP2C8Q208C8 40万们

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "K1P97 " "Info: Assuming node \"K1P97\" is an undefined clock" {  } { { "MCU8951.bdf" "" { Schematic "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/MCU8951.bdf" { { -536 232 440 -520 "K1P97" "" } } } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "K1P97" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "REG32B:inst12\|DOUT\[31\] " "Info: Detected ripple clock \"REG32B:inst12\|DOUT\[31\]\" as buffer" {  } { { "REG32B.vhd" "" { Text "G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/REG32B.vhd" 12 -1 0 } } { "e:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "e:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "REG32B:inst12\|DOUT\[31\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}