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📄 mcu8951.map.rpt

📁 KX_DVP3F型FPGA应用板/开发板(全套)包括: &#61592 CycloneII系列FPGA EP2C8Q208C8 40万们
💻 RPT
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字号:
; G1_MODE                       ; BYPASS            ; Untyped                      ;
; G2_MODE                       ; BYPASS            ; Untyped                      ;
; G3_MODE                       ; BYPASS            ; Untyped                      ;
; E0_MODE                       ; BYPASS            ; Untyped                      ;
; E1_MODE                       ; BYPASS            ; Untyped                      ;
; E2_MODE                       ; BYPASS            ; Untyped                      ;
; E3_MODE                       ; BYPASS            ; Untyped                      ;
; L0_PH                         ; 0                 ; Untyped                      ;
; L1_PH                         ; 0                 ; Untyped                      ;
; G0_PH                         ; 0                 ; Untyped                      ;
; G1_PH                         ; 0                 ; Untyped                      ;
; G2_PH                         ; 0                 ; Untyped                      ;
; G3_PH                         ; 0                 ; Untyped                      ;
; E0_PH                         ; 0                 ; Untyped                      ;
; E1_PH                         ; 0                 ; Untyped                      ;
; E2_PH                         ; 0                 ; Untyped                      ;
; E3_PH                         ; 0                 ; Untyped                      ;
; M_PH                          ; 0                 ; Untyped                      ;
; C1_USE_CASC_IN                ; 0                 ; Untyped                      ;
; C2_USE_CASC_IN                ; 0                 ; Untyped                      ;
; C3_USE_CASC_IN                ; 0                 ; Untyped                      ;
; C4_USE_CASC_IN                ; 0                 ; Untyped                      ;
; C5_USE_CASC_IN                ; 0                 ; Untyped                      ;
; CLK0_COUNTER                  ; G0                ; Untyped                      ;
; CLK1_COUNTER                  ; G0                ; Untyped                      ;
; CLK2_COUNTER                  ; G0                ; Untyped                      ;
; CLK3_COUNTER                  ; G0                ; Untyped                      ;
; CLK4_COUNTER                  ; G0                ; Untyped                      ;
; CLK5_COUNTER                  ; G0                ; Untyped                      ;
; L0_TIME_DELAY                 ; 0                 ; Untyped                      ;
; L1_TIME_DELAY                 ; 0                 ; Untyped                      ;
; G0_TIME_DELAY                 ; 0                 ; Untyped                      ;
; G1_TIME_DELAY                 ; 0                 ; Untyped                      ;
; G2_TIME_DELAY                 ; 0                 ; Untyped                      ;
; G3_TIME_DELAY                 ; 0                 ; Untyped                      ;
; E0_TIME_DELAY                 ; 0                 ; Untyped                      ;
; E1_TIME_DELAY                 ; 0                 ; Untyped                      ;
; E2_TIME_DELAY                 ; 0                 ; Untyped                      ;
; E3_TIME_DELAY                 ; 0                 ; Untyped                      ;
; M_TIME_DELAY                  ; 0                 ; Untyped                      ;
; N_TIME_DELAY                  ; 0                 ; Untyped                      ;
; EXTCLK3_COUNTER               ; E3                ; Untyped                      ;
; EXTCLK2_COUNTER               ; E2                ; Untyped                      ;
; EXTCLK1_COUNTER               ; E1                ; Untyped                      ;
; EXTCLK0_COUNTER               ; E0                ; Untyped                      ;
; ENABLE0_COUNTER               ; L0                ; Untyped                      ;
; ENABLE1_COUNTER               ; L0                ; Untyped                      ;
; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped                      ;
; LOOP_FILTER_R                 ;  1.000000         ; Untyped                      ;
; LOOP_FILTER_C                 ; 5                 ; Untyped                      ;
; VCO_POST_SCALE                ; 0                 ; Untyped                      ;
; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped                      ;
; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped                      ;
; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped                      ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II        ; Untyped                      ;
; PORT_CLKENA0                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKENA1                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKENA2                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKENA3                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKENA4                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKENA5                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_EXTCLK0                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_EXTCLK1                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_EXTCLK2                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_EXTCLK3                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKBAD0                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKBAD1                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLK0                     ; PORT_USED         ; Untyped                      ;
; PORT_CLK1                     ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLK2                     ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLK3                     ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLK4                     ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLK5                     ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCANDATA                 ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCANDATAOUT              ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCANDONE                 ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKLOSS                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_INCLK1                   ; PORT_UNUSED       ; Untyped                      ;
; PORT_INCLK0                   ; PORT_USED         ; Untyped                      ;
; PORT_FBIN                     ; PORT_UNUSED       ; Untyped                      ;
; PORT_PLLENA                   ; PORT_UNUSED       ; Untyped                      ;
; PORT_CLKSWITCH                ; PORT_UNUSED       ; Untyped                      ;
; PORT_ARESET                   ; PORT_UNUSED       ; Untyped                      ;
; PORT_PFDENA                   ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCANCLK                  ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCANACLR                 ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCANREAD                 ; PORT_UNUSED       ; Untyped                      ;
; PORT_SCANWRITE                ; PORT_UNUSED       ; Untyped                      ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                      ;
; PORT_LOCKED                   ; PORT_UNUSED       ; Untyped                      ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                      ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                      ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                      ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                      ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                      ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                      ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                      ;
; DEVICE_FAMILY                 ; Cyclone II        ; Untyped                      ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                   ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                 ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                 ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE               ;
+-------------------------------+-------------------+------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Feb 21 13:59:57 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MCU8951 -c MCU8951
Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/IRAM.VHD is missing
Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ROM4K.VHD is missing
Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/reg8b.vhd is missing
Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/ETESTER.VHD is missing
Warning: Can't analyze file -- file G:/KX-DVP2008.1/KX_DVP3F_new/DEMO1_KEY_LED/reg4b.vhd is missing
Info: Found 2 design units, including 1 entities, in source file DECODR.vhd
    Info: Found design unit 1: DECODR-one
    Info: Found entity 1: DECODR
Info: Found 2 design units, including 1 entities, in source file CNT4B.vhd
    Info: Found design unit 1: CNT4B-DACC
    Info: Found entity 1: CNT4B
Warning: Using design file MCU8951.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: MCU8951
Info: Elaborating entity "MCU8951" for the top level hierarchy
Info: Elaborating entity "CNT4B" for hierarchy "CNT4B:inst15"
Warning: Using design file REG32B.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: REG32B-behav
    Info: Found entity 1: REG32B
Info: Elaborating entity "REG32B" for hierarchy "REG32B:inst12"
Warning: Using design file pll2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: pll2-SYN
    Info: Found entity 1: pll2
Info: Elaborating entity "pll2" for hierarchy "pll2:inst13"
Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus60/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "pll2:inst13|altpll:altpll_component"
Info: Elaborated megafunction instantiation "pll2:inst13|altpll:altpll_component"
Warning: Using design file ADDER32B.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ADDER32B-behav
    Info: Found entity 1: ADDER32B
Info: Elaborating entity "ADDER32B" for hierarchy "ADDER32B:inst11"
Warning: Using design file CC.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project
    Info: Found design unit 1: CC_lpm_constant_lm8-RTL
    Info: Found design unit 2: cc-RTL
    Info: Found entity 1: CC_lpm_constant_lm8
    Info: Found entity 2: CC
Info: Elaborating entity "CC" for hierarchy "CC:inst14"
Info: Elaborating entity "CC_lpm_constant_lm8" for hierarchy "CC:inst14|CC_lpm_constant_lm8:CC_lpm_constant_lm8_component"
Warning: Reduced register "REG32B:inst12|DOUT[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "REG32B:inst12|DOUT[1]" with stuck data_in port to stuck value GND
Info: Implemented 65 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 16 output pins
    Info: Implemented 38 logic cells
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Thu Feb 21 14:00:00 2008
    Info: Elapsed time: 00:00:04


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