mcu8951.tan.rpt

KX_DVP3F型FPGA应用板/开发板（全套）包括： &#61592 CycloneII系列FPGA EP2C8Q208C8 40万们

; Total number of failed paths                             ;           ;                                  ;                                                ;                       ;                        ;                                           ;                                           ; 0            ;
+----------------------------------------------------------+-----------+----------------------------------+------------------------------------------------+-----------------------+------------------------+-------------------------------------------+-------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                            ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll2:inst13|altpll:altpll_component|_clk0 ;                    ; PLL output ; 30.0 MHz         ; 0.000 ns      ; 0.000 ns     ; CLK      ; 3                     ; 2                   ; -2.388 ns ;              ;
; CLK                                       ;                    ; User Pin   ; 20.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; K1P97                                     ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+-------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll2:inst13|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+------------------------+------------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                   ; To                     ; From Clock                                ; To Clock                                  ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------+------------------------+-------------------------------------------+-------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 28.482 ns                               ; 206.14 MHz ( period = 4.851 ns )                    ; REG32B:inst12|DOUT[2]  ; REG32B:inst12|DOUT[31] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.606 ns                ;
; 28.568 ns                               ; 209.86 MHz ( period = 4.765 ns )                    ; REG32B:inst12|DOUT[2]  ; REG32B:inst12|DOUT[30] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.520 ns                ;
; 28.654 ns                               ; 213.72 MHz ( period = 4.679 ns )                    ; REG32B:inst12|DOUT[2]  ; REG32B:inst12|DOUT[29] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.434 ns                ;
; 28.740 ns                               ; 217.72 MHz ( period = 4.593 ns )                    ; REG32B:inst12|DOUT[2]  ; REG32B:inst12|DOUT[28] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.348 ns                ;
; 28.820 ns                               ; 221.58 MHz ( period = 4.513 ns )                    ; REG32B:inst12|DOUT[3]  ; REG32B:inst12|DOUT[31] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.268 ns                ;
; 28.826 ns                               ; 221.88 MHz ( period = 4.507 ns )                    ; REG32B:inst12|DOUT[2]  ; REG32B:inst12|DOUT[27] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.262 ns                ;
; 28.860 ns                               ; 223.56 MHz ( period = 4.473 ns )                    ; REG32B:inst12|DOUT[4]  ; REG32B:inst12|DOUT[31] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.228 ns                ;
; 28.872 ns                               ; 224.16 MHz ( period = 4.461 ns )                    ; REG32B:inst12|DOUT[7]  ; REG32B:inst12|DOUT[31] ; pll2:inst13|altpll:altpll_component|_clk0 ; pll2:inst13|altpll:altpll_component|_clk0 ; 33.333 ns                   ; 33.088 ns                 ; 4.216 ns                ;