mcu8951.map.eqn

KX_DVP3F型FPGA应用板/开发板（全套）包括： &#61592 CycloneII系列FPGA EP2C8Q208C8 40万们

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_Q1[3] is CNT4B:inst15|Q1[3]
B1_Q1[3] = DFFEAS(B1L9, D1_DOUT[31],  ,  ,  ,  ,  ,  ,  );


--B1_Q1[2] is CNT4B:inst15|Q1[2]
B1_Q1[2] = DFFEAS(B1L7, D1_DOUT[31],  ,  ,  ,  ,  ,  ,  );


--B1_Q1[1] is CNT4B:inst15|Q1[1]
B1_Q1[1] = DFFEAS(B1L5, D1_DOUT[31],  ,  ,  ,  ,  ,  ,  );


--B1_Q1[0] is CNT4B:inst15|Q1[0]
B1_Q1[0] = DFFEAS(B1L3, D1_DOUT[31],  ,  ,  ,  ,  ,  ,  );


--B2_Q1[3] is CNT4B:inst|Q1[3]
B2_Q1[3] = DFFEAS(B2L9, K1P97,  ,  ,  ,  ,  ,  ,  );


--B2_Q1[2] is CNT4B:inst|Q1[2]
B2_Q1[2] = DFFEAS(B2L7, K1P97,  ,  ,  ,  ,  ,  ,  );


--B2_Q1[1] is CNT4B:inst|Q1[1]
B2_Q1[1] = DFFEAS(B2L5, K1P97,  ,  ,  ,  ,  ,  ,  );


--B2_Q1[0] is CNT4B:inst|Q1[0]
B2_Q1[0] = DFFEAS(B2L3, K1P97,  ,  ,  ,  ,  ,  ,  );


--B1L9 is CNT4B:inst15|Q1[3]~48
B1L9 = B1_Q1[3] $ (B1_Q1[2] & B1_Q1[1] & B1_Q1[0]);


--D1_DOUT[31] is REG32B:inst12|DOUT[31]
D1_DOUT[31] = DFFEAS(D1L90, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--B1L7 is CNT4B:inst15|Q1[2]~49
B1L7 = B1_Q1[2] $ (B1_Q1[1] & B1_Q1[0]);


--B1L5 is CNT4B:inst15|Q1[1]~50
B1L5 = B1_Q1[1] $ B1_Q1[0];


--B2L9 is CNT4B:inst|Q1[3]~48
B2L9 = B2_Q1[3] $ (B2_Q1[2] & B2_Q1[1] & B2_Q1[0]);


--B2L7 is CNT4B:inst|Q1[2]~49
B2L7 = B2_Q1[2] $ (B2_Q1[1] & B2_Q1[0]);


--B2L5 is CNT4B:inst|Q1[1]~50
B2L5 = B2_Q1[1] $ B2_Q1[0];


--G1__clk0 is pll2:inst13|altpll:altpll_component|_clk0
G1__clk0 = PLL.CLK0(.ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .INCLK(CLK), .INCLK());


--D1_DOUT[30] is REG32B:inst12|DOUT[30]
D1_DOUT[30] = DFFEAS(D1L87, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[29] is REG32B:inst12|DOUT[29]
D1_DOUT[29] = DFFEAS(D1L84, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[28] is REG32B:inst12|DOUT[28]
D1_DOUT[28] = DFFEAS(D1L81, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[27] is REG32B:inst12|DOUT[27]
D1_DOUT[27] = DFFEAS(D1L78, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[26] is REG32B:inst12|DOUT[26]
D1_DOUT[26] = DFFEAS(D1L75, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[25] is REG32B:inst12|DOUT[25]
D1_DOUT[25] = DFFEAS(D1L72, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[24] is REG32B:inst12|DOUT[24]
D1_DOUT[24] = DFFEAS(D1L69, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[23] is REG32B:inst12|DOUT[23]
D1_DOUT[23] = DFFEAS(D1L66, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[22] is REG32B:inst12|DOUT[22]
D1_DOUT[22] = DFFEAS(D1L63, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[21] is REG32B:inst12|DOUT[21]
D1_DOUT[21] = DFFEAS(D1L60, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[20] is REG32B:inst12|DOUT[20]
D1_DOUT[20] = DFFEAS(D1L57, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[19] is REG32B:inst12|DOUT[19]
D1_DOUT[19] = DFFEAS(D1L54, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[18] is REG32B:inst12|DOUT[18]
D1_DOUT[18] = DFFEAS(D1L51, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[17] is REG32B:inst12|DOUT[17]
D1_DOUT[17] = DFFEAS(D1L48, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[16] is REG32B:inst12|DOUT[16]
D1_DOUT[16] = DFFEAS(D1L45, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[15] is REG32B:inst12|DOUT[15]
D1_DOUT[15] = DFFEAS(D1L42, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[14] is REG32B:inst12|DOUT[14]
D1_DOUT[14] = DFFEAS(D1L39, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[13] is REG32B:inst12|DOUT[13]
D1_DOUT[13] = DFFEAS(D1L36, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[12] is REG32B:inst12|DOUT[12]
D1_DOUT[12] = DFFEAS(D1L33, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[11] is REG32B:inst12|DOUT[11]
D1_DOUT[11] = DFFEAS(D1L30, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[10] is REG32B:inst12|DOUT[10]
D1_DOUT[10] = DFFEAS(D1L27, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[9] is REG32B:inst12|DOUT[9]
D1_DOUT[9] = DFFEAS(D1L24, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[8] is REG32B:inst12|DOUT[8]
D1_DOUT[8] = DFFEAS(D1L21, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[7] is REG32B:inst12|DOUT[7]
D1_DOUT[7] = DFFEAS(D1L18, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[6] is REG32B:inst12|DOUT[6]
D1_DOUT[6] = DFFEAS(D1L15, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[5] is REG32B:inst12|DOUT[5]
D1_DOUT[5] = DFFEAS(D1L12, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[4] is REG32B:inst12|DOUT[4]
D1_DOUT[4] = DFFEAS(D1L9, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[3] is REG32B:inst12|DOUT[3]
D1_DOUT[3] = DFFEAS(D1L6, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1_DOUT[2] is REG32B:inst12|DOUT[2]
D1_DOUT[2] = DFFEAS(D1L3, G1__clk0,  ,  ,  ,  ,  ,  ,  );


--D1L3 is REG32B:inst12|DOUT[2]~242
D1L3 = D1_DOUT[2] $ VCC;

--D1L4 is REG32B:inst12|DOUT[2]~243
D1L4 = CARRY(D1_DOUT[2]);


--D1L6 is REG32B:inst12|DOUT[3]~244
D1L6 = D1_DOUT[3] & !D1L4 # !D1_DOUT[3] & (D1L4 # GND);

--D1L7 is REG32B:inst12|DOUT[3]~245
D1L7 = CARRY(!D1L4 # !D1_DOUT[3]);


--D1L9 is REG32B:inst12|DOUT[4]~246
D1L9 = D1_DOUT[4] & (GND # !D1L7) # !D1_DOUT[4] & (D1L7 $ GND);

--D1L10 is REG32B:inst12|DOUT[4]~247
D1L10 = CARRY(D1_DOUT[4] # !D1L7);


--D1L12 is REG32B:inst12|DOUT[5]~248
D1L12 = D1_DOUT[5] & D1L10 & VCC # !D1_DOUT[5] & !D1L10;

--D1L13 is REG32B:inst12|DOUT[5]~249
D1L13 = CARRY(!D1_DOUT[5] & !D1L10);


--D1L15 is REG32B:inst12|DOUT[6]~250
D1L15 = D1_DOUT[6] & (D1L13 $ GND) # !D1_DOUT[6] & !D1L13 & VCC;

--D1L16 is REG32B:inst12|DOUT[6]~251
D1L16 = CARRY(D1_DOUT[6] & !D1L13);


--D1L18 is REG32B:inst12|DOUT[7]~252
D1L18 = D1_DOUT[7] & D1L16 & VCC # !D1_DOUT[7] & !D1L16;

--D1L19 is REG32B:inst12|DOUT[7]~253
D1L19 = CARRY(!D1_DOUT[7] & !D1L16);


--D1L21 is REG32B:inst12|DOUT[8]~254
D1L21 = D1_DOUT[8] & (D1L19 $ GND) # !D1_DOUT[8] & !D1L19 & VCC;

--D1L22 is REG32B:inst12|DOUT[8]~255
D1L22 = CARRY(D1_DOUT[8] & !D1L19);


--D1L24 is REG32B:inst12|DOUT[9]~256
D1L24 = D1_DOUT[9] & !D1L22 # !D1_DOUT[9] & (D1L22 # GND);

--D1L25 is REG32B:inst12|DOUT[9]~257
D1L25 = CARRY(!D1L22 # !D1_DOUT[9]);


--D1L27 is REG32B:inst12|DOUT[10]~258
D1L27 = D1_DOUT[10] & (D1L25 $ GND) # !D1_DOUT[10] & !D1L25 & VCC;

--D1L28 is REG32B:inst12|DOUT[10]~259
D1L28 = CARRY(D1_DOUT[10] & !D1L25);


--D1L30 is REG32B:inst12|DOUT[11]~260
D1L30 = D1_DOUT[11] & !D1L28 # !D1_DOUT[11] & (D1L28 # GND);

--D1L31 is REG32B:inst12|DOUT[11]~261
D1L31 = CARRY(!D1L28 # !D1_DOUT[11]);


--D1L33 is REG32B:inst12|DOUT[12]~262
D1L33 = D1_DOUT[12] & (D1L31 $ GND) # !D1_DOUT[12] & !D1L31 & VCC;

--D1L34 is REG32B:inst12|DOUT[12]~263
D1L34 = CARRY(D1_DOUT[12] & !D1L31);


--D1L36 is REG32B:inst12|DOUT[13]~264
D1L36 = D1_DOUT[13] & !D1L34 # !D1_DOUT[13] & (D1L34 # GND);

--D1L37 is REG32B:inst12|DOUT[13]~265
D1L37 = CARRY(!D1L34 # !D1_DOUT[13]);


--D1L39 is REG32B:inst12|DOUT[14]~266
D1L39 = D1_DOUT[14] & (D1L37 $ GND) # !D1_DOUT[14] & !D1L37 & VCC;

--D1L40 is REG32B:inst12|DOUT[14]~267
D1L40 = CARRY(D1_DOUT[14] & !D1L37);


--D1L42 is REG32B:inst12|DOUT[15]~268
D1L42 = D1_DOUT[15] & !D1L40 # !D1_DOUT[15] & (D1L40 # GND);

--D1L43 is REG32B:inst12|DOUT[15]~269
D1L43 = CARRY(!D1L40 # !D1_DOUT[15]);


--D1L45 is REG32B:inst12|DOUT[16]~270
D1L45 = D1_DOUT[16] & (D1L43 $ GND) # !D1_DOUT[16] & !D1L43 & VCC;

--D1L46 is REG32B:inst12|DOUT[16]~271
D1L46 = CARRY(D1_DOUT[16] & !D1L43);


--D1L48 is REG32B:inst12|DOUT[17]~272
D1L48 = D1_DOUT[17] & !D1L46 # !D1_DOUT[17] & (D1L46 # GND);

--D1L49 is REG32B:inst12|DOUT[17]~273
D1L49 = CARRY(!D1L46 # !D1_DOUT[17]);


--D1L51 is REG32B:inst12|DOUT[18]~274
D1L51 = D1_DOUT[18] & (D1L49 $ GND) # !D1_DOUT[18] & !D1L49 & VCC;

--D1L52 is REG32B:inst12|DOUT[18]~275
D1L52 = CARRY(D1_DOUT[18] & !D1L49);


--D1L54 is REG32B:inst12|DOUT[19]~276
D1L54 = D1_DOUT[19] & !D1L52 # !D1_DOUT[19] & (D1L52 # GND);

--D1L55 is REG32B:inst12|DOUT[19]~277
D1L55 = CARRY(!D1L52 # !D1_DOUT[19]);


--D1L57 is REG32B:inst12|DOUT[20]~278
D1L57 = D1_DOUT[20] & (D1L55 $ GND) # !D1_DOUT[20] & !D1L55 & VCC;

--D1L58 is REG32B:inst12|DOUT[20]~279
D1L58 = CARRY(D1_DOUT[20] & !D1L55);


--D1L60 is REG32B:inst12|DOUT[21]~280
D1L60 = D1_DOUT[21] & !D1L58 # !D1_DOUT[21] & (D1L58 # GND);

--D1L61 is REG32B:inst12|DOUT[21]~281
D1L61 = CARRY(!D1L58 # !D1_DOUT[21]);


--D1L63 is REG32B:inst12|DOUT[22]~282
D1L63 = D1_DOUT[22] & (D1L61 $ GND) # !D1_DOUT[22] & !D1L61 & VCC;

--D1L64 is REG32B:inst12|DOUT[22]~283
D1L64 = CARRY(D1_DOUT[22] & !D1L61);


--D1L66 is REG32B:inst12|DOUT[23]~284
D1L66 = D1_DOUT[23] & !D1L64 # !D1_DOUT[23] & (D1L64 # GND);

--D1L67 is REG32B:inst12|DOUT[23]~285
D1L67 = CARRY(!D1L64 # !D1_DOUT[23]);


--D1L69 is REG32B:inst12|DOUT[24]~286
D1L69 = D1_DOUT[24] & (D1L67 $ GND) # !D1_DOUT[24] & !D1L67 & VCC;

--D1L70 is REG32B:inst12|DOUT[24]~287
D1L70 = CARRY(D1_DOUT[24] & !D1L67);


--D1L72 is REG32B:inst12|DOUT[25]~288
D1L72 = D1_DOUT[25] & !D1L70 # !D1_DOUT[25] & (D1L70 # GND);

--D1L73 is REG32B:inst12|DOUT[25]~289
D1L73 = CARRY(!D1L70 # !D1_DOUT[25]);


--D1L75 is REG32B:inst12|DOUT[26]~290
D1L75 = D1_DOUT[26] & (D1L73 $ GND) # !D1_DOUT[26] & !D1L73 & VCC;

--D1L76 is REG32B:inst12|DOUT[26]~291
D1L76 = CARRY(D1_DOUT[26] & !D1L73);


--D1L78 is REG32B:inst12|DOUT[27]~292
D1L78 = D1_DOUT[27] & !D1L76 # !D1_DOUT[27] & (D1L76 # GND);

--D1L79 is REG32B:inst12|DOUT[27]~293
D1L79 = CARRY(!D1L76 # !D1_DOUT[27]);


--D1L81 is REG32B:inst12|DOUT[28]~294
D1L81 = D1_DOUT[28] & (D1L79 $ GND) # !D1_DOUT[28] & !D1L79 & VCC;

--D1L82 is REG32B:inst12|DOUT[28]~295
D1L82 = CARRY(D1_DOUT[28] & !D1L79);


--D1L84 is REG32B:inst12|DOUT[29]~296
D1L84 = D1_DOUT[29] & !D1L82 # !D1_DOUT[29] & (D1L82 # GND);

--D1L85 is REG32B:inst12|DOUT[29]~297
D1L85 = CARRY(!D1L82 # !D1_DOUT[29]);


--D1L87 is REG32B:inst12|DOUT[30]~298
D1L87 = D1_DOUT[30] & (D1L85 $ GND) # !D1_DOUT[30] & !D1L85 & VCC;

--D1L88 is REG32B:inst12|DOUT[30]~299
D1L88 = CARRY(D1_DOUT[30] & !D1L85);


--D1L90 is REG32B:inst12|DOUT[31]~300
D1L90 = D1_DOUT[31] $ D1L88;


--B1L3 is CNT4B:inst15|Q1[0]~51
B1L3 = !B1_Q1[0];


--B2L3 is CNT4B:inst|Q1[0]~51
B2L3 = !B2_Q1[0];


--K5 is K5
--operation mode is input

K5 = INPUT();


--K6 is K6
--operation mode is input

K6 = INPUT();


--K7 is K7
--operation mode is input

K7 = INPUT();


--K8 is K8
--operation mode is input

K8 = INPUT();


--K9 is K9
--operation mode is input

K9 = INPUT();


--K10 is K10
--operation mode is input

K10 = INPUT();


--K11 is K11
--operation mode is input

K11 = INPUT();


--K12 is K12
--operation mode is input

K12 = INPUT();


--K1P97 is K1P97
--operation mode is input

K1P97 = INPUT();


--CLK is CLK
--operation mode is input

CLK = INPUT();


--D1 is D1
--operation mode is output

D1 = OUTPUT(!K5);


--D2 is D2
--operation mode is output

D2 = OUTPUT(!K6);


--D3 is D3
--operation mode is output

D3 = OUTPUT(!K7);


--D4 is D4
--operation mode is output

D4 = OUTPUT(!K8);


--D5 is D5
--operation mode is output

D5 = OUTPUT(!K9);


--D6 is D6
--operation mode is output

D6 = OUTPUT(!K10);


--D7 is D7
--operation mode is output

D7 = OUTPUT(!K11);


--D8 is D8
--operation mode is output

D8 = OUTPUT(!K12);


--LEDA[3] is LEDA[3]
--operation mode is output

LEDA[3] = OUTPUT(B1_Q1[3]);


--LEDA[2] is LEDA[2]
--operation mode is output

LEDA[2] = OUTPUT(B1_Q1[2]);


--LEDA[1] is LEDA[1]
--operation mode is output

LEDA[1] = OUTPUT(B1_Q1[1]);


--LEDA[0] is LEDA[0]
--operation mode is output

LEDA[0] = OUTPUT(B1_Q1[0]);


--LEDB[3] is LEDB[3]
--operation mode is output

LEDB[3] = OUTPUT(B2_Q1[3]);


--LEDB[2] is LEDB[2]
--operation mode is output

LEDB[2] = OUTPUT(B2_Q1[2]);


--LEDB[1] is LEDB[1]
--operation mode is output

LEDB[1] = OUTPUT(B2_Q1[1]);


--LEDB[0] is LEDB[0]
--operation mode is output

LEDB[0] = OUTPUT(B2_Q1[0]);