decodr.vhd

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LIBRARY IEEE ;
 USE IEEE.STD_LOGIC_1164.ALL ;
  ENTITY DECODR IS
    PORT ( A     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0) ;
           LED7S : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)  ) ;
 END ;
 ARCHITECTURE one OF DECODR IS
 BEGIN
     PROCESS( A )
    BEGIN
        CASE  A IS
          WHEN "0000" =>  LED7S <= "1000000" ; -- X"3F"à0
          WHEN "0001" =>  LED7S <= "1111001" ; -- X"06"à1
          WHEN "0010" =>  LED7S <= "0100100" ; -- X"5B"à2
          WHEN "0011" =>  LED7S <= "0110000" ; -- X"4F"à3
          WHEN "0100" =>  LED7S <= "0011001" ; -- X"66"à4
          WHEN "0101" =>  LED7S <= "0010010" ; -- X"6D"à5
          WHEN "0110" =>  LED7S <= "0000010" ; -- X"7D"à6
          WHEN "0111" =>  LED7S <= "1111000" ; -- X"07"à7
          WHEN "1000" =>  LED7S <= "0000000" ; -- X"7F"à8
          WHEN "1001" =>  LED7S <= "0010000" ; -- X"6F"à9
          WHEN "1010" =>  LED7S <= "0001000" ; -- X"77"à10
          WHEN "1011" =>  LED7S <= "0000011" ; -- X"7C"à11
          WHEN "1100" =>  LED7S <= "1000110" ; -- X"39"à12
          WHEN "1101" =>  LED7S <= "0100001" ; -- X"5E"à13
          WHEN "1110" =>  LED7S <= "0000110" ; -- X"79"à14
          WHEN "1111" =>  LED7S <= "0001110" ; -- X"71"à15
          WHEN OTHERS =>  NULL ;
        END CASE ;
    END PROCESS ;
 END ;