urisc1.vhd

URISC 处理器由数据单元和控制单元组成。数据单元中包含保存运算数据和运算结果的数据寄存器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;  -------------数学函数
use ieee.std_logic_unsigned.all;

--------------------处理器实体-------------------------不同的进程不能对同一个变量赋值！！
entity urisc1 is 
	port( datain: in  std_logic_vector(7 downto 0);
             dataout: out std_logic_vector(7 downto 0);
             address: out std_logic_vector(7 downto 0); 
                read: out std_logic;
               write: out std_logic;
             clk,run: in std_logic);
end urisc1;

------------------处理器结构体-------------------------

architecture behavior of urisc1 is
  signal r,rnot,busa,busb,mdr,mar: std_logic_vector(7 downto 0);
  signal pc: std_logic_vector(7 downto 0);
  signal pcin,pcout,rin,comp,cin,zin,nin,z,n,mdrin,mdrout,marin,zout,nout,zend,nnend,clk1,clk2,read1: std_logic;
  signal c: integer range -1 to 10;
  signal clear:std_logic;
  --variable m: std_logic;
begin
--------------------程序计数器-------------------------
PC_Reg: process (clk2,run)
begin
	if run='1'  then
             pc<="00000001";
	    
	elsif clk2'event and clk2='0' then
		if pcin='1' then 
			pc<=busb;
		end if;
		--if pcout='1' then
		--	busa<=pc;  --------------两个if同时进行
	        --end if;
	end if;
end process PC_Reg;
-----------------------BUS_A---------------------------------
process (pcout,mdrout,clk2) ---------额外控制信号
begin
	if(pcout='1') then
		busa<=pc;
	elsif(mdrout='1') then
		busa<=mdr;
	end if;
end process;

-------------------寄存器R----------------------------

R_Reg:process (clk2)
begin
	if clk2'event and clk2='0' then
		if rin='1' then
			r<=busa;
		     rnot<=not busa+1;
		end if;
	end if;
end process R_Reg;


----------------------rnot----------------------------
--R_NOT:process(r)
--begin
--	rnot<=not r+1;
--end process R_NOT;


-------------------加法器-------------------BUS_B-----------

add:process(busa,rnot,clk2)
begin
        
		if comp='0'and cin='1'  then
			busb<=busa+1;
		elsif comp='1'and cin='1'  then
			busb<=busa+rnot;
		--	nout<=busb(7);
		--	if busb="00000000"  then
		--		zout<='1';
		--	end if;
		elsif comp='0' and cin='0'  then
			busb<=busa; --zout<='0';
		end if;
	
end process add;

-----------------NOUT,ZOUT---------------------------
process (busb)
begin
     if busb="00000000"  then
	   zout<='1';
     else
	   zout<='0';
	   nout<=busb(7);
   end if;
   end process;
--------------------存储器N-------------------------------
N_Reg: process(clk2)
begin
	if clk2'event and clk2='0' then
		if nin='1' then
			n<=nout;
		end if;
	end if;
end process N_Reg;

--------------------存储器Z-------------------------------
Z_Reg:process(clk2)
begin
	if clk2'event and clk2='0' then
		if zin='1' then
			z<=zout;
		end if;
	end if;
end process Z_Reg;

-------------------- 数据存储器MDR1------------------------
MDR_Reg1: process (datain)
begin 
--	if clk1'event and clk1='0' then
		if read1='1' then
			mdr<=datain;
		end if;
--	end if;
end process MDR_Reg1;
--------------------数据寄存器MDR2------------------------
MDR_Reg2: process (clk1)
begin 
	if clk1'event and clk1='0' then
		if mdrin='1' then
			--mdr<=busb;
		        --data<=mdr;
			dataout<=busb;
		end if;
	end if;
end process MDR_Reg2;	
--------------------地址寄存器MAR-------------------------
MAR_Reg: process (clk2)
begin
	if clk2'event and clk2='0' then
		if marin='1' then
			address<=busb;
			mar<=busb;
		end if;
	end if;
end process MAR_Reg;

------------------计数器COUNTER----------------------------
Counter: process (clk1,run)
begin   
        
	if run='1'  then
	     c<= -1;
	elsif clk1'event and clk1='0' then
		if clear='0'	 then  
	       	     c<=c+1;
	        else
		     c<= 0;
	     end if;
	end if;
	
end process Counter;

-----------------------ROM----------------------------------

Rom: process (c)
	type sarray is array (0 to 8,0 to 13) of std_logic;
	----------------------pcin rin nin cin mdo mai wri zen nen pco com zin mdi red ----
	constant mem:sarray:=(('0','0','0','0','0','1','0','1','0','1','0','1','0','1'),
	                      ('0','0','0','0','1','1','0','0','0','0','0','0','0','1'),
                              ('0','1','0','0','1','0','0','0','0','0','0','0','0','0'),
                              ('1','0','0','1','0','1','0','0','0','1','0','0','0','1'),
                              ('0','0','0','0','1','1','0','0','0','0','0','0','0','1'),
                              ('0','0','1','1','1','0','1','0','0','0','1','0','1','0'),
                              ('1','0','0','1','0','1','0','0','0','1','0','0','0','1'),
                              ('1','0','0','1','0','0','0','0','1','1','0','0','0','0'),
                              ('1','0','0','0','1','0','0','0','0','0','0','0','0','0'));
begin
       
	if (c>-1) then  
	pcin<=mem((c),0);
	 rin<=mem((c),1);
	 nin<=mem((c),2);
	 cin<=mem((c),3);
      mdrout<=mem((c),4);
       marin<=mem((c),5);
       write<=mem((c),6);
	zend<=mem((c),7);
       nnend<=mem((c),8);
       pcout<=mem((c),9);
        comp<=mem((c),10);
         zin<=mem((c),11);
       mdrin<=mem((c),12);
        read<=mem((c),13);
       read1<=mem((c),13);
end if;
  end process Rom;         
----------------------清零-----------------------------------conv_integer
CLE: process(c,z,zend,n,nnend)

begin
      if (c=9) or ((z and zend)='1') or ((not n and nnend)='1')  then 
	       clear<='1';
      
       else
	       clear<='0';
       end if;

       end process CLE;

------------------------两相时钟---------------------------
CLOCK: process( run,clk)
	variable k: std_logic;
begin
	if run='1'  then
		k:='0';
		--m<='0';
		
	elsif clk'event and clk='1' then
		case k is
			when '0' => clk2<='1';clk1<='0';k:='1';--m<='1';
			when '1' => clk2<='0';clk1<='1';k:='0';--m<='0';
			when others => null;
		end case;
	end if;
end process CLOCK;	

end behavior;