hw1_inverter_startup.sp

self-biased voltage reference

* Bandgap Voltage Reference
* Set options
.option post probe
.include cmos06.mod
.param Ls=1.6u L0=3u W1=30u W2=20u r2=45k
m1 13 1 vdd vdd   cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m2 3 1 vdd vdd   cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m3 4 1 vdd vdd   cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m8 1 2 13 vdd     cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m9 5 2 3 vdd     cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m10 vref 2 4 vdd cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m4 7 6 9 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
m5 12 6 8 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
m6 2 5 7 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
m7 6 5 12 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
Rb1 1 2 142k -1.05e-3
Rb2 5 6 142k -1.05e-3
q1	vss	vss	10	bjtpnp	m=8
q2	vss vss	8	bjtpnp	m=1
q3	vss vss 11	bjtpnp	m=1
r1 9 10 10k	-1.05e-3
r2 vref 11 109.5k	-1.05e-3
*compensation camp
c2 vref vss 15p
c1 vdd 1 400f
*start-up ckt
mst1 st3 6 vdd vdd   cmosp w=0.6u      l=0.6u as='Ls*0.6u' ad='Ls*0.6u' ps='2*Ls+0.6u' pd='2*Ls+0.6u'
mst2 st2 6 vss vss   cmosn w=6u        l=0.6u as='Ls*6u' ad='Ls*6u' ps='2*Ls+6u' pd='2*Ls+6u'
mst3 1 st2 vss vss   cmosn w=6u        l=0.6u as='Ls*6u' ad='Ls*6u' ps='2*Ls+6u' pd='2*Ls+6u'
rst st3 st2 250k -1.05e-3
vdd	vdd	0	5	ac=1
vss vss 0 0
* Simulations for tempco, line regulation and supply current at different supply voltages
.dc	temp	-15	85	1	vdd	4.6	5.4	0.2
.probe	v(vref)	i(vdd) i(m1)
* Simulation for PSRR at different supply voltages
.ac	dec	100	1	10g	sweep	vdd	4.6	5.4	0.2
.probe	vdb(vref)
* Simulation for output noise at different supply voltages (defined at .ac statement)
.noise	v(vref)	vdd
.probe	onoise

*transient response
*vss vss 0 0
*vdd vdd 0 pwl(0 0 10n 5)
*.tran 1n 40u
*.probe v(vref)
.op
.end