hw1_razavi_startup.sp

来自「self-biased voltage reference」· SP 代码 · 共 59 行

* Bandgap Voltage Reference

* Set options
.option post probe
.include cmos06.mod
*.param Ls=1.6u L0=12u W1=120u W2=40u
*.param Ls=1.6u L0=6u W1=60u W2=20u
.param Ls=1.6u L0=3u W1=60u W2=30u 

m1 13 1 vdd vdd   cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m2 3 1 vdd vdd   cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m3 4 1 vdd vdd   cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m8 1 2 13 vdd     cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m9 5 2 3 vdd     cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m10 vref 2 4 vdd cmosp w=W1         l=L0 as='Ls*W1' ad='Ls*W1' ps='2*Ls+W1' pd='2*Ls+W1'
m4 7 6 9 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
m5 12 6 8 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
m6 2 5 7 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
m7 6 5 12 vss     cmosn w=W2         l='L0*2' as='Ls*W2' ad='Ls*W2' ps='2*Ls+W2' pd='2*Ls+W2'
Rb1 1 2 142k -1.05e-3
Rb2 5 6 142k -1.05e-3
c2 vref vss 2.5p
c1 vdd 1 400f
q1	vss	vss	10	bjtpnp	m=8
q2	vss vss	8	bjtpnp	m=1
q3	vss vss 11	bjtpnp	m=1
r1 9 10 15k	-1.05e-3
r2 vref 11 167k	-1.05e-3


*start-up ckt
mst1 st2 st1 vss vss   cmosn w=6u       l=0.6u as='Ls*0.6u' ad='Ls*0.6u' ps='2*Ls+0.6u' pd='2*Ls+0.6u'
mst2 1 st2 vss vss   cmosn w=800u       l=0.6u as='Ls*0.6u' ad='Ls*0.6u' ps='2*Ls+0.6u' pd='2*Ls+0.6u'
rst1 vdd st1 300k  -1.05e-3
rst2 st1 st2 60k  -1.05e-3


vdd	vdd	0	5	ac=1
vss vss 0 0




* Simulations for tempco, line regulation and supply current at different supply voltages
.dc	temp	-15	85	1	vdd	4.6	5.4	0.2
.probe	v(vref)	i(vdd) i(m1)

* Simulation for PSRR at different supply voltages
*.ac	dec	100	1	10g	sweep	vdd	4.6	5.4	0.2
*.probe	vdb(vref)

* Simulation for output noise at different supply voltages (defined at .ac statement)
*.noise	v(vref)	vdd
*.probe	onoise

.op

.end