clock.tan.qmsg

一个用verilog编写的数字时钟

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 6 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dataout_buf\[0\]\[0\] register dataout_buf\[7\]\[3\] 86.87 MHz 11.512 ns Internal " "Info: Clock \"clk\" has Internal fmax of 86.87 MHz between source register \"dataout_buf\[0\]\[0\]\" and destination register \"dataout_buf\[7\]\[3\]\" (period= 11.512 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.803 ns + Longest register register " "Info: + Longest register to register delay is 10.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dataout_buf\[0\]\[0\] 1 REG LC_X9_Y8_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y8_N5; Fanout = 6; REG Node = 'dataout_buf\[0\]\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "" { dataout_buf[0][0] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.993 ns) + CELL(0.914 ns) 1.907 ns reduce_nor~1054 2 COMB LC_X9_Y8_N8 2 " "Info: 2: + IC(0.993 ns) + CELL(0.914 ns) = 1.907 ns; Loc. = LC_X9_Y8_N8; Fanout = 2; COMB Node = 'reduce_nor~1054'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.907 ns" { dataout_buf[0][0] reduce_nor~1054 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.794 ns) + CELL(0.511 ns) 4.212 ns dataout_buf\[6\]\[3\]~1409 3 COMB LC_X11_Y8_N0 8 " "Info: 3: + IC(1.794 ns) + CELL(0.511 ns) = 4.212 ns; Loc. = LC_X11_Y8_N0; Fanout = 8; COMB Node = 'dataout_buf\[6\]\[3\]~1409'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "2.305 ns" { reduce_nor~1054 dataout_buf[6][3]~1409 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.735 ns) + CELL(0.740 ns) 5.687 ns dataout_buf\[3\]\[3\]~1411 4 COMB LC_X11_Y8_N1 6 " "Info: 4: + IC(0.735 ns) + CELL(0.740 ns) = 5.687 ns; Loc. = LC_X11_Y8_N1; Fanout = 6; COMB Node = 'dataout_buf\[3\]\[3\]~1411'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.475 ns" { dataout_buf[6][3]~1409 dataout_buf[3][3]~1411 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.733 ns) + CELL(0.200 ns) 6.620 ns dataout_buf\[7\]\[3\]~1417 5 COMB LC_X11_Y8_N9 3 " "Info: 5: + IC(0.733 ns) + CELL(0.200 ns) = 6.620 ns; Loc. = LC_X11_Y8_N9; Fanout = 3; COMB Node = 'dataout_buf\[7\]\[3\]~1417'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "0.933 ns" { dataout_buf[3][3]~1411 dataout_buf[7][3]~1417 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.743 ns) + CELL(0.200 ns) 7.563 ns dataout_buf\[7\]\[3\]~1418 6 COMB LC_X11_Y8_N2 1 " "Info: 6: + IC(0.743 ns) + CELL(0.200 ns) = 7.563 ns; Loc. = LC_X11_Y8_N2; Fanout = 1; COMB Node = 'dataout_buf\[7\]\[3\]~1418'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "0.943 ns" { dataout_buf[7][3]~1417 dataout_buf[7][3]~1418 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.997 ns) + CELL(1.243 ns) 10.803 ns dataout_buf\[7\]\[3\] 7 REG LC_X11_Y7_N5 2 " "Info: 7: + IC(1.997 ns) + CELL(1.243 ns) = 10.803 ns; Loc. = LC_X11_Y7_N5; Fanout = 2; REG Node = 'dataout_buf\[7\]\[3\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "3.240 ns" { dataout_buf[7][3]~1418 dataout_buf[7][3] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.808 ns 35.25 % " "Info: Total cell delay = 3.808 ns ( 35.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.995 ns 64.75 % " "Info: Total interconnect delay = 6.995 ns ( 64.75 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "10.803 ns" { dataout_buf[0][0] reduce_nor~1054 dataout_buf[6][3]~1409 dataout_buf[3][3]~1411 dataout_buf[7][3]~1417 dataout_buf[7][3]~1418 dataout_buf[7][3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.803 ns" { dataout_buf[0][0] reduce_nor~1054 dataout_buf[6][3]~1409 dataout_buf[3][3]~1411 dataout_buf[7][3]~1417 dataout_buf[7][3]~1418 dataout_buf[7][3] } { 0.000ns 0.993ns 1.794ns 0.735ns 0.733ns 0.743ns 1.997ns } { 0.000ns 0.914ns 0.511ns 0.740ns 0.200ns 0.200ns 1.243ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.739 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 74 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.689 ns) + CELL(0.918 ns) 6.739 ns dataout_buf\[7\]\[3\] 2 REG LC_X11_Y7_N5 2 " "Info: 2: + IC(4.689 ns) + CELL(0.918 ns) = 6.739 ns; Loc. = LC_X11_Y7_N5; Fanout = 2; REG Node = 'dataout_buf\[7\]\[3\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "5.607 ns" { clk dataout_buf[7][3] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.42 % " "Info: Total cell delay = 2.050 ns ( 30.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.689 ns 69.58 % " "Info: Total interconnect delay = 4.689 ns ( 69.58 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk dataout_buf[7][3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout dataout_buf[7][3] } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.739 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 74 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.689 ns) + CELL(0.918 ns) 6.739 ns dataout_buf\[0\]\[0\] 2 REG LC_X9_Y8_N5 6 " "Info: 2: + IC(4.689 ns) + CELL(0.918 ns) = 6.739 ns; Loc. = LC_X9_Y8_N5; Fanout = 6; REG Node = 'dataout_buf\[0\]\[0\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "5.607 ns" { clk dataout_buf[0][0] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.42 % " "Info: Total cell delay = 2.050 ns ( 30.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.689 ns 69.58 % " "Info: Total interconnect delay = 4.689 ns ( 69.58 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk dataout_buf[0][0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout dataout_buf[0][0] } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk dataout_buf[7][3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout dataout_buf[7][3] } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk dataout_buf[0][0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout dataout_buf[0][0] } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "10.803 ns" { dataout_buf[0][0] reduce_nor~1054 dataout_buf[6][3]~1409 dataout_buf[3][3]~1411 dataout_buf[7][3]~1417 dataout_buf[7][3]~1418 dataout_buf[7][3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.803 ns" { dataout_buf[0][0] reduce_nor~1054 dataout_buf[6][3]~1409 dataout_buf[3][3]~1411 dataout_buf[7][3]~1417 dataout_buf[7][3]~1418 dataout_buf[7][3] } { 0.000ns 0.993ns 1.794ns 0.735ns 0.733ns 0.743ns 1.997ns } { 0.000ns 0.914ns 0.511ns 0.740ns 0.200ns 0.200ns 1.243ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk dataout_buf[7][3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout dataout_buf[7][3] } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk dataout_buf[0][0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout dataout_buf[0][0] } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[7\] en\[3\]~reg0 22.012 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[7\]\" through register \"en\[3\]~reg0\" is 22.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.739 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.739 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 74 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 74; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "" { clk } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.689 ns) + CELL(0.918 ns) 6.739 ns en\[3\]~reg0 2 REG LC_X9_Y7_N7 7 " "Info: 2: + IC(4.689 ns) + CELL(0.918 ns) = 6.739 ns; Loc. = LC_X9_Y7_N7; Fanout = 7; REG Node = 'en\[3\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "5.607 ns" { clk en[3]~reg0 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns 30.42 % " "Info: Total cell delay = 2.050 ns ( 30.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.689 ns 69.58 % " "Info: Total interconnect delay = 4.689 ns ( 69.58 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk en[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout en[3]~reg0 } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.897 ns + Longest register pin " "Info: + Longest register to pin delay is 14.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[3\]~reg0 1 REG LC_X9_Y7_N7 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N7; Fanout = 7; REG Node = 'en\[3\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "" { en[3]~reg0 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.914 ns) 2.408 ns reduce_nor~1042 2 COMB LC_X9_Y7_N1 2 " "Info: 2: + IC(1.494 ns) + CELL(0.914 ns) = 2.408 ns; Loc. = LC_X9_Y7_N1; Fanout = 2; COMB Node = 'reduce_nor~1042'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "2.408 ns" { en[3]~reg0 reduce_nor~1042 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.832 ns) + CELL(0.200 ns) 4.440 ns reduce_nor~15 3 COMB LC_X11_Y7_N8 4 " "Info: 3: + IC(1.832 ns) + CELL(0.200 ns) = 4.440 ns; Loc. = LC_X11_Y7_N8; Fanout = 4; COMB Node = 'reduce_nor~15'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "2.032 ns" { reduce_nor~1042 reduce_nor~15 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.766 ns) + CELL(0.200 ns) 6.406 ns dataout_code\[0\]~736 4 COMB LC_X13_Y7_N6 1 " "Info: 4: + IC(1.766 ns) + CELL(0.200 ns) = 6.406 ns; Loc. = LC_X13_Y7_N6; Fanout = 1; COMB Node = 'dataout_code\[0\]~736'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.966 ns" { reduce_nor~15 dataout_code[0]~736 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.705 ns) + CELL(0.914 ns) 8.025 ns dataout_code\[0\]~737 5 COMB LC_X13_Y7_N3 8 " "Info: 5: + IC(0.705 ns) + CELL(0.914 ns) = 8.025 ns; Loc. = LC_X13_Y7_N3; Fanout = 8; COMB Node = 'dataout_code\[0\]~737'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.619 ns" { dataout_code[0]~736 dataout_code[0]~737 } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.382 ns) + CELL(0.511 ns) 9.918 ns reduce_or~88 6 COMB LC_X12_Y7_N5 1 " "Info: 6: + IC(1.382 ns) + CELL(0.511 ns) = 9.918 ns; Loc. = LC_X12_Y7_N5; Fanout = 1; COMB Node = 'reduce_or~88'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "1.893 ns" { dataout_code[0]~737 reduce_or~88 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.657 ns) + CELL(2.322 ns) 14.897 ns dataout\[7\] 7 PIN PIN_109 0 " "Info: 7: + IC(2.657 ns) + CELL(2.322 ns) = 14.897 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'dataout\[7\]'" {  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "4.979 ns" { reduce_or~88 dataout[7] } "NODE_NAME" } "" } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/clock.v" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.061 ns 33.97 % " "Info: Total cell delay = 5.061 ns ( 33.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.836 ns 66.03 % " "Info: Total interconnect delay = 9.836 ns ( 66.03 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "14.897 ns" { en[3]~reg0 reduce_nor~1042 reduce_nor~15 dataout_code[0]~736 dataout_code[0]~737 reduce_or~88 dataout[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.897 ns" { en[3]~reg0 reduce_nor~1042 reduce_nor~15 dataout_code[0]~736 dataout_code[0]~737 reduce_or~88 dataout[7] } { 0.000ns 1.494ns 1.832ns 1.766ns 0.705ns 1.382ns 2.657ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.914ns 0.511ns 2.322ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "6.739 ns" { clk en[3]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.739 ns" { clk clk~combout en[3]~reg0 } { 0.000ns 0.000ns 4.689ns } { 0.000ns 1.132ns 0.918ns } } } { "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock_cmp.qrpt" Compiler "clock" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/db/clock.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/EDA主板/max1270/示例程序/veriloge/综合实验/数字时钟/" "" "14.897 ns" { en[3]~reg0 reduce_nor~1042 reduce_nor~15 dataout_code[0]~736 dataout_code[0]~737 reduce_or~88 dataout[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "14.897 ns" { en[3]~reg0 reduce_nor~1042 reduce_nor~15 dataout_code[0]~736 dataout_code[0]~737 reduce_or~88 dataout[7] } { 0.000ns 1.494ns 1.832ns 1.766ns 0.705ns 1.382ns 2.657ns } { 0.000ns 0.914ns 0.200ns 0.200ns 0.914ns 0.511ns 2.322ns } } }  } 0}