clock.map.summary

来自「一个用verilog编写的数字时钟」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Sat Feb 18 13:48:10 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 174
Total pins : 18
Total virtual pins : 0
UFM blocks : 0