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📄 security.psm

📁 基于spartan3e的串口调试和检测程序,可直接烧写,检测结果将同时通过LCD显示出来
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                          ; KCPSM3 Program - Security control and design authentication.
                          ;
                          ; This program is provided for use with the reference design
                          ; 'low_cost_design_authentication_for_spartan_3e.vhd' implemented on the Spartan-3E Starter
                          ; Kit. The program provides design authentication control over the 'real' application as well
                          ; as providing features to enable evaluation of the design authentication method.
                          ;
                          ; Ken Chapman - Xilinx Ltd
                          ;
                          ; Version v1.00 - 1st November 2006
                          ;
                          ; This code communicates with the StrataFLASH memory to implement a design authentication
                          ; algorithm which then enables the main application design in various ways. To facilitate
                          ; evaluation of design authentication this design also interacts with the LCD display
                          ; and PC (via UART based RS232 link) to indicate authentication status and allow control
                          ; over the authentication validity of the design. Therefore this program includes:-
                          ;
                          ; 1) Code required to check authorisation which would be included in a production design.
                          ; 2) Code required to program the authentication value into FLASH memory which would
                          ;    typically only be implemented in a special design used at a secure programming
                          ;    facility as part of the production programming procedure.
                          ; 3) Code to allow you to see what is happening at all stages which is code that should
                          ;    never be included in a real production design as it reveals secrets that should remain
                          ;    hidden in order to make the task of breaking the security as difficult as possible.
                          ;
                          ; IMPORTANT - Feel free to use this code as a reference for your own security scheme but
                          ;             never use this code unmodified.
                          ;
                          ;
                          ;**************************************************************************************
                          ; NOTICE:
                          ;
                          ; Copyright Xilinx, Inc. 2006.   This code may be contain portions patented by other
                          ; third parties.  By providing this core as one possible implementation of a standard,
                          ; Xilinx is making no representation that the provided implementation of this standard
                          ; is free from any claims of infringement by any third party.  Xilinx expressly
                          ; disclaims any warranty with respect to the adequacy of the implementation, including
                          ; but not limited to any warranty or representation that the implementation is free
                          ; from claims of any third party.  Furthermore, Xilinx is providing this core as a
                          ; courtesy to you and suggests that you contact all third parties to obtain the
                          ; necessary rights to use this implementation.
                          ;
                          ;
                          ;**************************************************************************************
                          ; Port definitions
                          ;**************************************************************************************
                          ;
                          ;
                          ; UART ports
                          ;
                          ; Connection to PC to allow display of progress information and to operate simple
                          ; menu of commands.
                          ;
                          CONSTANT status_port, 00                 ;UART and memory status
                          CONSTANT tx_half_full, 01                ;  Transmitter     half full - bit0
                          CONSTANT tx_full, 02                     ;    FIFO            tx_full - bit1
                          CONSTANT rx_data_present, 04             ;  Receiver     data present - bit2
                          CONSTANT rx_half_full, 08                ;    FIFO          half full - bit3
                          CONSTANT rx_full, 10                     ;                    rx_full - bit4
                          CONSTANT spare1, 20                      ;                  spare '0' - bit5
                          CONSTANT spare2, 40                      ;                  spare '0' - bit6
                          CONSTANT strataflash_sts, 80             ;  StrataFLASH           STS - bit7
                          ;
                          CONSTANT UART_read_port, 01              ;UART Rx data input
                          ;
                          CONSTANT UART_write_port, 08             ;UART Tx data output
                          ;
                          ;
                          ; LCD Display
                          ;
                          ;The master enable signal is not used by the LCD display itself
                          ;but is used to prevent any contention with the StrataFLASH memory that
                          ;is connected to the same data pins. In this design the StrataFLASH memory is
                          ;used in 8-bit mode so not contention should exist but this master enable
                          ;facilty is then available for anyone wanting to modify the design for use
                          ;with a 16-bit interface.
                          ;
                          CONSTANT LCD_output_port, 20             ;LCD character module output data and control
                          CONSTANT LCD_E, 01                       ;   active High Enable        E - bit0
                          CONSTANT LCD_RW, 02                      ;   Read=1 Write=0           RW - bit1
                          CONSTANT LCD_RS, 04                      ;   Instruction=0 Data=1     RS - bit2
                          CONSTANT LCD_drive, 08                   ;   Master enable (active High) - bit3
                          CONSTANT LCD_DB4, 10                     ;   4-bit              Data DB4 - bit4
                          CONSTANT LCD_DB5, 20                     ;   interface          Data DB5 - bit5
                          CONSTANT LCD_DB6, 40                     ;                      Data DB6 - bit6
                          CONSTANT LCD_DB7, 80                     ;                      Data DB7 - bit7
                          ;
                          ;
                          CONSTANT LCD_input_port, 03              ;LCD character module input data
                          CONSTANT LCD_read_spare0, 01             ;    Spare bits               - bit0
                          CONSTANT LCD_read_spare1, 02             ;    are zero                 - bit1
                          CONSTANT LCD_read_spare2, 04             ;                             - bit2
                          CONSTANT LCD_read_spare3, 08             ;                             - bit3
                          CONSTANT LCD_read_DB4, 10                ;    4-bit           Data DB4 - bit4
                          CONSTANT LCD_read_DB5, 20                ;    interface       Data DB5 - bit5
                          CONSTANT LCD_read_DB6, 40                ;                    Data DB6 - bit6
                          CONSTANT LCD_read_DB7, 80                ;                    Data DB7 - bit7
                          ;
                          ;
                          ;
                          ; StrataFLASH memory ports
                          ;
                          ; The FLASH memory is used to hold the authentication value as well as provide the
                          ; unique serial number from which the authentication algorithm computes the value.
                          ; In practice, the FLASH will also hold the configuration image for the Spartan device.
                          ;
                          ;
                          CONSTANT SF_data_in_port, 02             ;Read data from StrataFLASH device
                          ;
                          CONSTANT SF_data_out_port, 80            ;Data to write into StrataFLASH device
                          ;
                          CONSTANT SF_addr_hi_port, 83             ;StrataFLASH address[21:16] (6 LSB's)
                          CONSTANT SF_addr_mi_port, 82             ;StrataFLASH address[15:8]
                          CONSTANT SF_addr_lo_port, 81             ;StrataFLASH address[7:0]
                          ;
                          CONSTANT SF_control_port, 40             ;StrataFLASH control
                          CONSTANT SF_read, 01                     ;         active High read - bit0
                          CONSTANT SF_ce, 02                       ; active Low device enable - bit1
                          CONSTANT SF_we, 04                       ;         active Low write - bit2
                          ;
                          ;
                          ; Design Authentication enable/disable signals.
                          ;
                          ; Hardware controls over the 'real' application.
                          ;
                          CONSTANT authentication_control_port, 10 ;Design disable control port
                          CONSTANT security_disable_interrupts, 01 ;   active High disable of interrupt generation - bit0
                          CONSTANT security_disable_outputs, 02    ;            active High disable of output pins - bit1
                          ;
                          ; Pseudo Random number generator
                          ;
                          CONSTANT random_value_port, 04           ;read LFSR counter value
                          ;
                          ;
                          ; Link FIFO buffer
                          ;
                          ; Provides a connection to the 'real' application such that 'soft tokens' in the
                          ; form of short messages to be passed to the 'real' application to enable or disable
                          ; it depending on the authentication status.
                          ;
                          CONSTANT link_FIFO_write_port, 04        ;write data to FIFO
                          ;
                          ;
                          ;**************************************************************************************
                          ; Special Register usage
                          ;**************************************************************************************
                          ;
                          NAMEREG sF, UART_data                    ;used to pass data to and from the UART
                          ;
                          ;
                          ;
                          ;**************************************************************************************
                          ;Scratch Pad Memory Locations
                          ;**************************************************************************************
                          ;
                          CONSTANT ISR_preserve_s0, 00             ;preserve register contents during Interrupt Service Routine
                          ;
                          ;
                          CONSTANT serial_number0, 10              ;64-bit serial number of StrataFlash
                          CONSTANT serial_number1, 11              ;LS-Byte first
                          CONSTANT serial_number2, 12
                          CONSTANT serial_number3, 13
                          CONSTANT serial_number4, 14
                          CONSTANT serial_number5, 15
                          CONSTANT serial_number6, 16
                          CONSTANT serial_number7, 17
                          ;
                          ;
                          CONSTANT computed_CRC0, 18               ;computed 16-bit CRC based on the
                          CONSTANT computed_CRC1, 19               ;  StrataFlash unique serial number (LS-Byte first)
                          ;
                          ;
                          CONSTANT authentication_CRC0, 1A         ;16-bit CRC value read from authentication
                          CONSTANT authentication_CRC1, 1B         ;  area of StrataFLASH memory (LS-Byte first)
                          ;
                          ;
                          CONSTANT authentication_status, 1C       ;Status of design authentication
                          ;
                          ;
                          ;**************************************************************************************
                          ;Useful data constants
                          ;**************************************************************************************
                          ;
                          ;
                          ;
                          ;Constant to define a software delay of 1us. This must be adjusted to reflect the
                          ;clock applied to KCPSM3. Every instruction executes in 2 clock cycles making the
                          ;calculation highly predictable. The '6' in the following equation even allows for
                          ;'CALL delay_1us' instruction in the initiating code.
                          ;
                          ; delay_1us_constant =  (clock_rate - 6)/4       Where 'clock_rate' is in MHz
                          ;
                          ;Example: For a 50MHz clock the constant value is (10-6)/4 = 11  (0B Hex).
                          ;For clock rates below 10MHz the value of 1 must be used and the operation will

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