📄 liangzhu.map.rpt
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; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 81 ;
; -- arithmetic mode ; 42 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 14 ;
; -- asynchronous clear/load mode ; 24 ;
; ; ;
; Total registers ; 64 ;
; Total logic cells in carry chains ; 45 ;
; I/O pins ; 3 ;
; Total memory bits ; 1024 ;
; Maximum fan-out node ; clk_cnt[23] ;
; Maximum fan-out ; 30 ;
; Total fan-out ; 490 ;
; Average fan-out ; 3.77 ;
+---------------------------------------------+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+---------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------+
; |liangzhu ; 123 (123) ; 64 ; 1024 ; 0 ; 3 ; 0 ; 59 (59) ; 5 (5) ; 59 (59) ; 45 (45) ; 0 (0) ; |liangzhu ;
; |altsyncram:WideOr13_rtl_0| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |liangzhu|altsyncram:WideOr13_rtl_0 ;
; |altsyncram_3iu:auto_generated| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |liangzhu|altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated ;
+---------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+--------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-------------------+
; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 256 ; 4 ; -- ; -- ; 1024 ; liangzhu0.rtl.mif ;
+--------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+-------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 64 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 14 ;
; Number of registers using Asynchronous Clear ; 24 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------------------------------------+
; Source assignments for altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated ;
+---------------------------------+--------------------+------+------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
+---------------------------------+--------------------+------+------------------+
+----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altsyncram:WideOr13_rtl_0 ;
+------------------------------------+-------------------+-------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+-------------------+-------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 4 ; Untyped ;
; WIDTHAD_A ; 8 ; Untyped ;
; NUMWORDS_A ; 256 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; liangzhu0.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_3iu ; Untyped ;
+------------------------------------+-------------------+-------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Tue Jul 22 02:35:48 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off liangzhu -c liangzhu
Info: Found 1 design units, including 1 entities, in source file liangzhu.v
Info: Found entity 1: liangzhu
Info: Elaborating entity "liangzhu" for the top level hierarchy
Warning: Reduced register "high[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "high[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "high[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "med[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "low[3]" with stuck data_in port to stuck value GND
Info: Inferred 1 megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=4) from the following design logic: "WideOr13~1"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Elaborated megafunction instantiation "altsyncram:WideOr13_rtl_0"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3iu.tdf
Info: Found entity 1: altsyncram_3iu
Info: Implemented 130 device resources after synthesis - the final resource count might be different
Info: Implemented 2 input pins
Info: Implemented 1 output pins
Info: Implemented 123 logic cells
Info: Implemented 4 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Processing ended: Tue Jul 22 02:35:51 2008
Info: Elapsed time: 00:00:03
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