liangzhu.fit.qmsg

FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用

{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.572 ns memory register " "Info: Estimated most critical path is memory to register delay of 9.572 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg7 1 MEM M4K_X17_Y12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|ram_block1a3~porta_address_reg7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg7 } "NODE_NAME" } } { "db/altsyncram_3iu.tdf" "" { Text "E:/alteraFPAG/liangzhu/db/altsyncram_3iu.tdf" 97 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|q_a\[3\] 2 MEM M4K_X17_Y12 11 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y12; Fanout = 11; MEM Node = 'altsyncram:WideOr13_rtl_0\|altsyncram_3iu:auto_generated\|q_a\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.308 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg7 altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[3] } "NODE_NAME" } } { "db/altsyncram_3iu.tdf" "" { Text "E:/alteraFPAG/liangzhu/db/altsyncram_3iu.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.114 ns) 5.873 ns Equal10~107 3 COMB LAB_X23_Y12 7 " "Info: 3: + IC(1.451 ns) + CELL(0.114 ns) = 5.873 ns; Loc. = LAB_X23_Y12; Fanout = 7; COMB Node = 'Equal10~107'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.565 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[3] Equal10~107 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.302 ns) + CELL(0.590 ns) 6.765 ns Equal7~101 4 COMB LAB_X22_Y12 3 " "Info: 4: + IC(0.302 ns) + CELL(0.590 ns) = 6.765 ns; Loc. = LAB_X22_Y12; Fanout = 3; COMB Node = 'Equal7~101'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.892 ns" { Equal10~107 Equal7~101 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.114 ns) 7.418 ns WideNor0~102 5 COMB LAB_X22_Y12 5 " "Info: 5: + IC(0.539 ns) + CELL(0.114 ns) = 7.418 ns; Loc. = LAB_X22_Y12; Fanout = 5; COMB Node = 'WideNor0~102'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Equal7~101 WideNor0~102 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.590 ns) 8.071 ns WideNor0~106 6 COMB LAB_X22_Y12 3 " "Info: 6: + IC(0.063 ns) + CELL(0.590 ns) = 8.071 ns; Loc. = LAB_X22_Y12; Fanout = 3; COMB Node = 'WideNor0~106'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { WideNor0~102 WideNor0~106 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 8.724 ns origin~84 7 COMB LAB_X22_Y12 3 " "Info: 7: + IC(0.361 ns) + CELL(0.292 ns) = 8.724 ns; Loc. = LAB_X22_Y12; Fanout = 3; COMB Node = 'origin~84'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { WideNor0~106 origin~84 } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.539 ns) + CELL(0.309 ns) 9.572 ns origin\[1\] 8 REG LAB_X22_Y12 1 " "Info: 8: + IC(0.539 ns) + CELL(0.309 ns) = 9.572 ns; Loc. = LAB_X22_Y12; Fanout = 1; REG Node = 'origin\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.848 ns" { origin~84 origin[1] } "NODE_NAME" } } { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.317 ns ( 65.99 % ) " "Info: Total cell delay = 6.317 ns ( 65.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.255 ns ( 34.01 % ) " "Info: Total interconnect delay = 3.255 ns ( 34.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.572 ns" { altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg7 altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|q_a[3] Equal10~107 Equal7~101 WideNor0~102 WideNor0~106 origin~84 origin[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y11 x23_y21 " "Info: The peak interconnect region extends from location x12_y11 to location x23_y21" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 22 02:35:55 2008 " "Info: Processing ended: Tue Jul 22 02:35:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/alteraFPAG/liangzhu/liangzhu.fit.smsg " "Info: Generated suppressed messages file E:/alteraFPAG/liangzhu/liangzhu.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}