liangzhu.map.qmsg

FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 22 02:35:48 2008 " "Info: Processing started: Tue Jul 22 02:35:48 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off liangzhu -c liangzhu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off liangzhu -c liangzhu" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "liangzhu.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file liangzhu.v" { { "Info" "ISGN_ENTITY_NAME" "1 liangzhu " "Info: Found entity 1: liangzhu" {  } { { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "liangzhu " "Info: Elaborating entity \"liangzhu\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "high\[3\] data_in GND " "Warning: Reduced register \"high\[3\]\" with stuck data_in port to stuck value GND" {  } { { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "high\[2\] data_in GND " "Warning: Reduced register \"high\[2\]\" with stuck data_in port to stuck value GND" {  } { { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "high\[1\] data_in GND " "Warning: Reduced register \"high\[1\]\" with stuck data_in port to stuck value GND" {  } { { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "med\[3\] data_in GND " "Warning: Reduced register \"med\[3\]\" with stuck data_in port to stuck value GND" {  } { { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "low\[3\] data_in GND " "Warning: Reduced register \"low\[3\]\" with stuck data_in port to stuck value GND" {  } { { "liangzhu.v" "" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 110 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_ROM_INFERRED" "WideOr13~1 256 4 " "Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=256, WIDTH_A=4) from the following design logic: \"WideOr13~1\"" {  } { { "liangzhu.v" "WideOr13~1" { Text "E:/alteraFPAG/liangzhu/liangzhu.v" 59 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 426 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "altsyncram:WideOr13_rtl_0 " "Info: Elaborated megafunction instantiation \"altsyncram:WideOr13_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3iu.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3iu.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3iu " "Info: Found entity 1: altsyncram_3iu" {  } { { "db/altsyncram_3iu.tdf" "" { Text "E:/alteraFPAG/liangzhu/db/altsyncram_3iu.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "130 " "Info: Implemented 130 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "123 " "Info: Implemented 123 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "4 " "Info: Implemented 4 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 22 02:35:51 2008 " "Info: Processing ended: Tue Jul 22 02:35:51 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}