liangzhu.fit.rpt

FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用

; Perform Asynchronous Signal Pipelining             ; Off                            ; Off                            ;
; Fitter Effort                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication           ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Auto                           ; Auto                           ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/alteraFPAG/liangzhu/liangzhu.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 118 / 5,980 ( 2 % )    ;
;     -- Combinational with no register       ; 54                     ;
;     -- Register only                        ; 0                      ;
;     -- Combinational with a register        ; 64                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 46                     ;
;     -- 3 input functions                    ; 9                      ;
;     -- 2 input functions                    ; 58                     ;
;     -- 1 input functions                    ; 5                      ;
;     -- 0 input functions                    ; 0                      ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 76                     ;
;     -- arithmetic mode                      ; 42                     ;
;     -- qfbk mode                            ; 4                      ;
;     -- register cascade mode                ; 0                      ;
;     -- synchronous clear/load mode          ; 18                     ;
;     -- asynchronous clear/load mode         ; 24                     ;
;                                             ;                        ;
; Total LABs                                  ; 14 / 598 ( 2 % )       ;
; Logic elements in carry chains              ; 45                     ;
; User inserted logic elements                ; 0                      ;
; Virtual pins                                ; 0                      ;
; I/O pins                                    ; 3 / 185 ( 2 % )        ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )         ;
; Global signals                              ; 4                      ;
; M4Ks                                        ; 1 / 20 ( 5 % )         ;
; Total memory bits                           ; 1,024 / 92,160 ( 1 % ) ;
; Total RAM block bits                        ; 4,608 / 92,160 ( 5 % ) ;
; PLLs                                        ; 0 / 2 ( 0 % )          ;
; Global clocks                               ; 4 / 8 ( 50 % )         ;
; Maximum fan-out node                        ; clk_cnt[23]            ;
; Maximum fan-out                             ; 27                     ;
; Highest non-global fan-out signal           ; Equal0~166             ;
; Highest non-global fan-out                  ; 15                     ;
; Total fan-out                               ; 471                    ;
; Average fan-out                             ; 3.80                   ;
+---------------------------------------------+------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LogicLock Region Resource Usage                                                                                                                                                                           ;
+------------------+--------+-------+--------+-------------+--------------+-------------+-------+-------+--------------+--------------+-------------------+------------------+-----------------+------------+
; LogicLock Region ; Origin ; Width ; Height ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks  ; Pins  ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ;
+------------------+--------+-------+--------+-------------+--------------+-------------+-------+-------+--------------+--------------+-------------------+------------------+-----------------+------------+
; Root Region      ; X0_Y0  ; 36    ; 22     ; 0 (0)       ; 0 (0)        ; 0 (0)       ; 0 (0) ; 0 (0) ; 0 (0)        ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ;
+------------------+--------+-------+--------+-------------+--------------+-------------+-------+-------+--------------+--------------+-------------------+------------------+-----------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                    ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; rst_n   ; 65    ; 4        ; 4            ; 0            ; 1           ; 24                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; sys_clk ; 28    ; 1        ; 0            ; 12           ; 2           ; 24                    ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                             ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load  ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+
; sp   ; 66    ; 4        ; 4            ; 0            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; 10 pF ;
+------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+


+----------------------------------------------------------+
; I/O Bank Usage                                           ;
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage          ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
; 1        ; 3 / 44 ( 7 % ) ; 3.3V          ; --           ;
; 2        ; 0 / 48 ( 0 % ) ; 3.3V          ; --           ;
; 3        ; 0 / 45 ( 0 % ) ; 3.3V          ; --           ;
; 4        ; 2 / 48 ( 4 % ) ; 3.3V          ; --           ;
+----------+----------------+---------------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; All Package Pins                                                                                                                                                        ;