liangzhu.tan.summary

FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.850 ns
From           : sp~reg0
To             : sp
From Clock     : sys_clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'sys_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 96.86 MHz ( period = 10.324 ns )
From           : altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg7
To             : origin[4]
From Clock     : sys_clk
To Clock       : sys_clk
Failed Paths   : 0

Type           : Clock Hold: 'sys_clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : sp~reg0
To             : sp~reg0
From Clock     : sys_clk
To Clock       : sys_clk
Failed Paths   : 1

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1

--------------------------------------------------------------------------------------