liangzhu.tan.rpt

FPGA开发入门的Verilog HDL程序2---梁祝音乐播放,真实可用

; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; sys_clk         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sys_clk'                                                                                                                                                                                                                                                                                           ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                    ; To         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg1 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg2 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg3 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg4 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg5 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg6 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.86 MHz ( period = 10.324 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg7 ; origin[4]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.626 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg1 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg2 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg3 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg4 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg5 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg6 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.89 MHz ( period = 10.321 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg7 ; origin[1]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.623 ns                ;
; N/A                                     ; 96.90 MHz ( period = 10.320 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg0 ; origin[3]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.622 ns                ;
; N/A                                     ; 96.90 MHz ( period = 10.320 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg1 ; origin[3]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.622 ns                ;
; N/A                                     ; 96.90 MHz ( period = 10.320 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg2 ; origin[3]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.622 ns                ;
; N/A                                     ; 96.90 MHz ( period = 10.320 ns )                    ; altsyncram:WideOr13_rtl_0|altsyncram_3iu:auto_generated|ram_block1a3~porta_address_reg3 ; origin[3]  ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.622 ns                ;