数字钟电路程序.doc

这个程序主要介绍了数字钟用VHDL的写法

        end if;
     end process;
     glitter<=q(21);
     sec<=q(21)and not dly;                   --微分产生1HZ
     ss<=q(15 downto 13);                     --about250HZ
     sample<=q(14)and not sdly;               --取样信号
                                              --扫描信号
     sel<="111110"when ss=0 else
            "111101"when ss=1 else
            "111001"when ss=2 else
            "110111"when ss=3 else
            "101111"when ss=4 else
            "011111"when ss=5 else
            "111111";
      en<="001"when(ss=0 or ss=1)else
            "010"when(ss=2 or ss=3)else
            "100"when(ss=4 or ss=5)else
            "000";
       bin<=dbs when en="001"else             --选择秒、分、时
              dbm when en="010"else
              dbh when en="100"else
              "000000";
       match<='1'when((ss=0 or ss=1)and state="10")else 
                  '1'when((ss=2 or ss=3) and state="01")else
                  '1'when((ss=4 or ss=5)and state="00")else
                  '0';
       s<=ss;
       enb<=en;
end behavioral;
BINARY_BCD.VHD                               --二进制与BCD码转换模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity binary_bcd is
    port(bin:in std_logic_vector(5 downto 0);
           bcd:out std_logic_vector(7 downto 0););
end binary_bcd;
architecture behavioral of binary_bcd is
begin                                          --二进制与BCD码的转换
    bcd<="00000000"when bin=0 else
            "00000001"when bin=1 else
            "00000010"when bin=2 else
            "00000011"when bin=3 else
            "00000100"when bin=4 else
            "00000101"when bin=5 else
            "00000110"when bin=6 else
            "00000111"when bin=7 else
            "00001000"when bin=8 else            
            "00001001"when bin=9 else
            "00010000"when bin=10 else
            "00010001"when bin=11 else
            "00010010"when bin=12 else
            "00010011"when bin=13 else
            "00010100"when bin=14 else
            "00010101"when bin=15 else
            "00010110"when bin=16 else
            "00010111"when bin=17 else
            "00011000"when bin=18 else
            "00011001"when bin=19 else
            "00100000"when bin=20 else
            "00100001"when bin=21 else
            "00100010"when bin=22 else
            "00100011"when bin=23 else
            "00100100"when bin=24 else
            "00100101"when bin=25 else
            "00100110"when bin=26 else
            "00100111"when bin=27 else
            "00101000"when bin=28 else
            "00101001"when bin=29 else
            "00110000"when bin=30 else
            "00110001"when bin=31 else
            "00110010"when bin=32 else
            "00110011"when bin=33 else
            "00110100"when bin=34 else
            "00110101"when bin=35 else
            "00110110"when bin=36 else
            "00110111"when bin=37 else
            "00111000"when bin=38 else
            "00111001"when bin=39 else
            "01000000"when bin=40 else
            "01000001"when bin=41 else
            "01000010"when bin=42 else
            "01000011"when bin=43 else
            "01000100"when bin=44 else
            "01000101"when bin=45 else
            "01000110"when bin=46 else
            "01000111"when bin=47 else
            "01001000"when bin=48 else
            "01001001"when bin=49 else
            "01010000"when bin=50 else
            "01010001"when bin=51 else
            "01010010"when bin=52 else
            "01010011"when bin=53 else
            "01010100"when bin=54 else
            "01010101"when bin=55 else
            "01010110"when bin=56 else
            "01010111"when bin=57 else
            "01011000"when bin=58 else
            "01011001"when bin=59 else
            "00000000";
end behavioral;
SEVEN_SEGMENT.VHD                            --七段数码显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seven_segment is
   port( num:in std_logic_vector(3 downto 0);
         seg:out std_logic_vector(6 downto 0));
end seven_segment;
architecture behavioral of seven_segment is --Binary Code->Segment7Code
begin
         seg<="0111111"when num=0 else
              "0000110"when num=1 else
              "1011011"when num=2 else
              "1001111"when num=3 else
              "1100110"when num=4 else
              "1101101"when num=5 else
              "1111101"when num=6 else
              "0000111"when num=7 else
              "1111111"when num=8 else
              "1101111"when num=9 else
              "1110111"when num=10 else
              "1111100"when num=11 else
              "0111001"when num=12 else
              "1011110"when num=13 else
              "1111001"when num=14 else
              "1110001"when num=15 else
              "0000000";
end behavioral;
DEBOUNCE.VHD                                       --消除弹跳电路模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity debounce is 
     port(cp:in std_logic;
           sample:in std_logic;
           key:in std_logic_vector(2 downto 0);
           dly_out:out std_logic);
end debounce;
architecture behavioral of debounce is
     signal d0,d1,s,r,dly,ndly:std_logic;
begin
     process(cp)
     begin
         if cp'event and cp='1'then
            if sample='1'then
               d1<=d0;d0<=key(2);                     --二级延迟
               s<=d0 and d1;
               r<=not d0 and not d1;
           end if;
         end if;
    end process;
    dly<=r nor ndly;                            --RS触发器
ndly<=s nor dly;                                      
dly_out<=dly;                               --RS触发器输出
end behavioral;
DIFFERENTIAL.VHD                               --BCD码选择器模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity differential is
      port(cp:in std_logic;
             dly_out:in std_logic;
             diff:out std_logic);              --SEG7 DISPLAY O/P
end differential;
architecture behavioral of differential is 
      signal d1,d0:std_logic;
begin
      process(cp)
      begin
           if cp'event and cp='1'then
              d1<=d0;d0<=dly_out;              --二级延迟
           end if;
      end process;
      diff<=d0 and not d1;                     --微分
end behavioral;
TIMERSET.VHD                                    --预置数模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity timerset is                           --SEC&Min&Hr Adjustment?
    port(cp:in std_logic;                                     
         diff:in std_logic;                                  
         key:in std_logic_vector(2 downto 0);                 
         state:out std_logic_vector(1 downto 0));
end timerset;
architecture behavioral of timerset is 
    signal q:std_logic_vector(2 downto 0);
    signal set,ec:std_logic;
begin
    process(cp)
    begin
            if set='1'then
                  q<="011";
            elsif cp'event and cp='1' then
                  if ec='1'then
                    q<=q-1;
                  end if;
            end if;
    end process;
    set<='1'when q=7 else
         '0';
    ec<=diff and key(2);                         --TIMER KEY 微分
    state<=q(1 downto 0);                        --Record Timer State
end behavioral;