__projnav.log

具有LCD显示单元的可编程单脉冲发生器的硬件实现

Writing ONE_PULSE_LCD.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ONE_PULSE_LCD.prj"
Compiling include file "ONE_PULSE_LCD.v"
Compiling include file "ONE_PULSE.v"
Module <ONE_PULSE> compiled
Module <LD_EN_DCNT> compiled
Module <P_DLY> compiled
Module <DELAY> compiled
Module <P_DETECT> compiled
Module <DFF_R1> compiled
Module <DFF_R> compiled
Module <TFF> compiled
Compiling include file "BIN_BCD_LCD.v"
ERROR:HDLCompilers:208 - BIN_BCD_LCD.v line 2 Port reference 'A' was not declared as input, inout or output
Module <BIN_BCD_LCD> compiled
Module <CNT> compiled
Module <LCD> compiled
Module <BIN_BCD> compiled
Module <ONE_PULSE_LCD> compiled
Compiling include file "D:/Xilinx52/verilog/src/iSE/unisim_comp.v"
Analysis of file <ONE_PULSE_LCD.prj> failed.
CPU : 0.26 / 0.58 s | Elapsed : 0.00 / 0.00 s
 
--> 

Total memory usage is 44096 kilobytes


Error: XST failed
Reason: 

Completed process "Synthesize".


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "ONE_PULSE_LCD.prj"
Compiling include file "ONE_PULSE_LCD.v"
Compiling include file "ONE_PULSE.v"
Module <ONE_PULSE> compiled
Module <LD_EN_DCNT> compiled
Module <P_DLY> compiled
Module <DELAY> compiled
Module <P_DETECT> compiled
Module <DFF_R1> compiled
Module <DFF_R> compiled
Module <TFF> compiled
Compiling include file "BIN_BCD_LCD.v"
Module <BIN_BCD_LCD> compiled
Module <CNT> compiled
Module <LCD> compiled
Module <BIN_BCD> compiled
Module <ONE_PULSE_LCD> compiled
Compiling include file "D:/Xilinx52/verilog/src/iSE/unisim_comp.v"
WARNING:HDLCompilers:94 - ONE_PULSE_LCD.v line 21 Connection to input port 2 does not match port size
No errors in compilation

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analysis of file <ONE_PULSE_LCD.prj> succeeded.
 
 
Analyzing module <DFF_R1>.
Module <DFF_R1> is correct for synthesis.
 
Analyzing module <DELAY>.
Module <DELAY> is correct for synthesis.
 
Analyzing module <TFF>.
Module <TFF> is correct for synthesis.
 
Analyzing module <P_DLY>.
Module <P_DLY> is correct for synthesis.
 
Analyzing module <LD_EN_DCNT>.
Module <LD_EN_DCNT> is correct for synthesis.
 
Analyzing module <DFF_R>.
Module <DFF_R> is correct for synthesis.
 
Analyzing module <P_DETECT>.
Module <P_DETECT> is correct for synthesis.
 
Analyzing module <ONE_PULSE>.
Module <ONE_PULSE> is correct for synthesis.
 
Analyzing module <CNT>.
Module <CNT> is correct for synthesis.
 
Analyzing module <BIN_BCD>.
Module <BIN_BCD> is correct for synthesis.
 
Analyzing module <LCD>.
WARNING:Xst:905 - BIN_BCD_LCD.v line 68: The signals <NUMW, NUMQ, NUMB, NUMS, NUMG> are missing in the sensitivity list of always block.
Module <LCD> is correct for synthesis.
 
Analyzing module <BIN_BCD_LCD>.
Module <BIN_BCD_LCD> is correct for synthesis.
 
Analyzing top module <ONE_PULSE_LCD>.
Module <ONE_PULSE_LCD> is correct for synthesis.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <DFF_R1>.
    Related source file is ONE_PULSE.v.
    Found 1-bit register for signal <Q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <DFF_R1> synthesized.


Synthesizing Unit <DELAY>.
    Related source file is ONE_PULSE.v.
    Found 3-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <DELAY> synthesized.


Synthesizing Unit <TFF>.
    Related source file is ONE_PULSE.v.
    Found 1-bit register for signal <QB>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <TFF> synthesized.


Synthesizing Unit <P_DLY>.
    Related source file is ONE_PULSE.v.
Unit <P_DLY> synthesized.


Synthesizing Unit <LD_EN_DCNT>.
    Related source file is ONE_PULSE.v.
    Found 8-bit down counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <LD_EN_DCNT> synthesized.


Synthesizing Unit <DFF_R>.
    Related source file is ONE_PULSE.v.
    Found 1-bit register for signal <Q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <DFF_R> synthesized.


Synthesizing Unit <P_DETECT>.
    Related source file is ONE_PULSE.v.
Unit <P_DETECT> synthesized.


Synthesizing Unit <ONE_PULSE>.
    Related source file is ONE_PULSE.v.
Unit <ONE_PULSE> synthesized.


Synthesizing Unit <CNT>.
    Related source file is BIN_BCD_LCD.v.
    Found 16-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <CNT> synthesized.


Synthesizing Unit <BIN_BCD>.
    Related source file is BIN_BCD_LCD.v.
WARNING:Xst:646 - Signal <C> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<19>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<18>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<17>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<16>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<15>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<14>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<13>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<12>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<11>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<10>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<9>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<8>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<7>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<6>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<5>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<4>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<3>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<2>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<1>> is assigned but never used.
WARNING:Xst:646 - Signal <TEMP<0>> is assigned but never used.
WARNING:Xst:646 - Signal <I> is assigned but never used.
    Found 4-bit register for signal <BB>.
    Found 4-bit register for signal <BG>.
    Found 4-bit register for signal <BQ>.
    Found 4-bit register for signal <BS>.
    Found 4-bit register for signal <BW>.
    Found 4-bit adder for signal <$n0000> created at line 117.
    Found 4-bit adder for signal <$n0001> created at line 121.
    Found 4-bit adder for signal <$n0002> created at line 125.
    Found 4-bit adder for signal <$n0003> created at line 129.
    Found 4-bit adder for signal <$n0004> created at line 133.
    Found 4-bit adder for signal <$n0024> created at line 117.
    Found 4-bit adder for signal <$n0025> created at line 121.
    Found 4-bit adder for signal <$n0026> created at line 125.
    Found 4-bit adder for signal <$n0027> created at line 129.
    Found 4-bit adder for signal <$n0028> created at line 133.
    Found 4-bit adder for signal <$n0048> created at line 117.
    Found 4-bit adder for signal <$n0049> created at line 121.
    Found 4-bit adder for signal <$n0050> created at line 125.
    Found 4-bit adder for signal <$n0051> created at line 129.
    Found 4-bit adder for signal <$n0052> created at line 133.
    Found 4-bit adder for signal <$n0072> created at line 117.
    Found 4-bit adder for signal <$n0073> created at line 121.
    Found 4-bit adder for signal <$n0074> created at line 125.
    Found 4-bit adder for signal <$n0075> created at line 129.
    Found 4-bit adder for signal <$n0076> created at line 133.
    Found 4-bit adder for signal <$n0096> created at line 117.
    Found 4-bit adder for signal <$n0097> created at line 121.
    Found 4-bit adder for signal <$n0098> created at line 125.
    Found 4-bit adder for signal <$n0099> created at line 129.
    Found 4-bit adder for signal <$n0100> created at line 133.
    Found 4-bit adder for signal <$n0120> created at line 117.
    Found 4-bit adder for signal <$n0121> created at line 121.
    Found 4-bit adder for signal <$n0122> created at line 125.
    Found 4-bit adder for signal <$n0123> created at line 129.
    Found 4-bit adder for signal <$n0124> created at line 133.
    Found 4-bit adder for signal <$n0144> created at line 117.
    Found 4-bit adder for signal <$n0145> created at line 121.
    Found 4-bit adder for signal <$n0146> created at line 125.
    Found 4-bit adder for signal <$n0147> created at line 129.
    Found 4-bit adder for signal <$n0148> created at line 133.
    Found 4-bit adder for signal <$n0168> created at line 117.
    Found 4-bit adder for signal <$n0169> created at line 121.
    Found 4-bit adder for signal <$n0170> created at line 125.
    Found 4-bit adder for signal <$n0171> created at line 129.
    Found 4-bit adder for signal <$n0172> created at line 133.
    Found 4-bit adder for signal <$n0192> created at line 117.
    Found 4-bit adder for signal <$n0193> created at line 121.
    Found 4-bit adder for signal <$n0194> created at line 125.
    Found 4-bit adder for signal <$n0195> created at line 129.
    Found 4-bit adder for signal <$n0196> created at line 133.
    Found 4-bit adder for signal <$n0216> created at line 117.
    Found 4-bit adder for signal <$n0217> created at line 121.
    Found 4-bit adder for signal <$n0218> created at line 125.
    Found 4-bit adder for signal <$n0219> created at line 129.
    Found 4-bit adder for signal <$n0220> created at line 133.
    Found 4-bit adder for signal <$n0240> created at line 117.
    Found 4-bit adder for signal <$n0241> created at line 121.
    Found 4-bit adder for signal <$n0242> created at line 125.
    Found 4-bit adder for signal <$n0243> created at line 129.
    Found 4-bit adder for signal <$n0244> created at line 133.
    Found 4-bit adder for signal <$n0264> created at line 117.
    Found 4-bit adder for signal <$n0265> created at line 121.
    Found 4-bit adder for signal <$n0266> created at line 125.
    Found 4-bit adder for signal <$n0267> created at line 129.
    Found 4-bit adder for signal <$n0268> created at line 133.
    Found 4-bit adder for signal <$n0288> created at line 117.
    Found 4-bit adder for signal <$n0289> created at line 121.
    Found 4-bit adder for signal <$n0290> created at line 125.
    Found 4-bit adder for signal <$n0291> created at line 129.
    Found 4-bit adder for signal <$n0292> created at line 133.
    Found 4-bit adder for signal <$n0312> created at line 117.
    Found 4-bit adder for signal <$n0313> created at line 121.
    Found 4-bit adder for signal <$n0314> created at line 125.
    Found 4-bit adder for signal <$n0315> created at line 129.
    Found 4-bit adder for signal <$n0316> created at line 133.
    Found 4-bit adder for signal <$n0336> created at line 117.
    Found 4-bit adder for signal <$n0337> created at line 121.
    Found 4-bit adder for signal <$n0338> created at line 125.
    Found 4-bit adder for signal <$n0339> created at line 129.
    Found 4-bit adder for signal <$n0340> created at line 133.
    Found 4-bit adder for signal <$n0360> created at line 117.
    Found 4-bit adder for signal <$n0361> created at line 121.
    Found 4-bit adder for signal <$n0362> created at line 125.
    Found 4-bit adder for signal <$n0363> created at line 129.
    Found 4-bit adder for signal <$n0364> created at line 133.
    Found 4-bit comparator greater for signal <$n0384> created at line 131.
    Found 4-bit comparator greater for signal <$n0385> created at line 127.
    Found 4-bit comparator greater for signal <$n0386> created at line 123.
    Found 4-bit comparator greater for signal <$n0387> created at line 119.
    Found 4-bit comparator greater for signal <$n0388> created at line 115.
    Found 4-bit comparator greater for signal <$n0389> created at line 131.
    Found 4-bit comparator greater for signal <$n0390> created at line 127.
    Found 4-bit comparator greater for signal <$n0391> created at line 123.
    Found 4-bit comparator greater for signal <$n0392> created at line 119.
    Found 4-bit comparator greater for signal <$n0393> created at line 115.
    Found 4-bit comparator greater for signal <$n0394> created at line 131.
    Found 4-bit comparator greater for signal <$n0395> created at line 127.
    Found 4-bit comparator greater for signal <$n0396> created at line 123.
    Found 4-bit comparator greater for signal <$n0397> created at line 119.
    Found 4-bit comparator greater for signal <$n0398> created at line 115.
    Found 4-bit comparator greater for signal <$n0399> created at line 131.