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具有LCD显示单元的可编程单脉冲发生器的硬件实现

Analyzing module <CNT>.
Module <CNT> is correct for synthesis.
 
Analyzing module <BIN_BCD>.
	Enabling task <INB>.
	Enabling task <INB>.
	Enabling task <INB>.
Module <BIN_BCD> is correct for synthesis.
 
Analyzing module <LCD>.
WARNING:Xst:905 - BIN_BCD_LCD.v line 68: The signals <NUMB, NUMS, NUMG> are missing in the sensitivity list of always block.
Module <LCD> is correct for synthesis.
 
Analyzing module <BIN_BCD_LCD>.
Module <BIN_BCD_LCD> is correct for synthesis.
 
Analyzing top module <ONE_PULSE_LCD>.
Module <ONE_PULSE_LCD> is correct for synthesis.
WARNING:Xst:39 - Property "BOX_TYPE" not applicable on a signal.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <DFF_R1>.
    Related source file is ONE_PULSE.v.
    Found 1-bit register for signal <Q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <DFF_R1> synthesized.


Synthesizing Unit <DELAY>.
    Related source file is ONE_PULSE.v.
    Found 3-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <DELAY> synthesized.


Synthesizing Unit <TFF>.
    Related source file is ONE_PULSE.v.
    Found 1-bit register for signal <QB>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <TFF> synthesized.


Synthesizing Unit <P_DLY>.
    Related source file is ONE_PULSE.v.
Unit <P_DLY> synthesized.


Synthesizing Unit <LD_EN_DCNT>.
    Related source file is ONE_PULSE.v.
    Found 8-bit down counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <LD_EN_DCNT> synthesized.


Synthesizing Unit <DFF_R>.
    Related source file is ONE_PULSE.v.
    Found 1-bit register for signal <Q>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <DFF_R> synthesized.


Synthesizing Unit <P_DETECT>.
    Related source file is ONE_PULSE.v.
Unit <P_DETECT> synthesized.


Synthesizing Unit <ONE_PULSE>.
    Related source file is ONE_PULSE.v.
Unit <ONE_PULSE> synthesized.


Synthesizing Unit <CNT>.
    Related source file is BIN_BCD_LCD.v.
    Found 16-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <CNT> synthesized.


Synthesizing Unit <BIN_BCD>.
    Related source file is BIN_BCD_LCD.v.
WARNING:Xst:646 - Signal <MS> is assigned but never used.
    Found 4-bit register for signal <BB>.
    Found 4-bit register for signal <BG>.
    Found 4-bit register for signal <BS>.
    Found 8-bit comparator less for signal <$n0000> created at line 163.
    Found 8-bit comparator less for signal <$n0001> created at line 169.
    Found 4-bit subtractor for signal <$n0004>.
    Found 8-bit comparator less for signal <$n0008> created at line 105.
    Found 8-bit comparator less for signal <$n0009> created at line 110.
    Found 8-bit comparator less for signal <$n0010> created at line 115.
    Found 8-bit comparator less for signal <$n0011> created at line 120.
    Found 8-bit comparator less for signal <$n0012> created at line 125.
    Found 8-bit comparator less for signal <$n0013> created at line 130.
    Found 8-bit comparator less for signal <$n0014> created at line 135.
    Found 8-bit comparator less for signal <$n0015> created at line 140.
    Found 8-bit comparator less for signal <$n0016> created at line 145.
    Found 8-bit comparator less for signal <$n0017> created at line 105.
    Found 8-bit comparator less for signal <$n0018> created at line 110.
    Found 8-bit comparator less for signal <$n0019> created at line 115.
    Found 8-bit comparator less for signal <$n0020> created at line 120.
    Found 8-bit comparator less for signal <$n0021> created at line 125.
    Found 8-bit comparator less for signal <$n0022> created at line 130.
    Found 8-bit comparator less for signal <$n0023> created at line 135.
    Found 8-bit comparator less for signal <$n0024> created at line 140.
    Found 8-bit comparator less for signal <$n0025> created at line 145.
    Found 8-bit comparator less for signal <$n0026> created at line 105.
    Found 8-bit comparator less for signal <$n0027> created at line 110.
    Found 8-bit comparator less for signal <$n0028> created at line 115.
    Found 8-bit comparator less for signal <$n0029> created at line 120.
    Found 8-bit comparator less for signal <$n0030> created at line 125.
    Found 8-bit comparator less for signal <$n0031> created at line 130.
    Found 8-bit comparator less for signal <$n0032> created at line 135.
    Found 8-bit comparator less for signal <$n0033> created at line 140.
    Found 8-bit comparator less for signal <$n0034> created at line 145.
    Found 8-bit subtractor for signal <$old_MS_1>.
    Found 8-bit subtractor for signal <$old_MS_2>.
    Found 8-bit subtractor for signal <$old_MS_3>.
    Summary:
	inferred   4 Adder/Subtracter(s).
	inferred  29 Comparator(s).
Unit <BIN_BCD> synthesized.


Synthesizing Unit <LCD>.
    Related source file is BIN_BCD_LCD.v.
WARNING:Xst:737 - Found 4-bit latch for signal <P>.
WARNING:Xst:737 - Found 5-bit latch for signal <LD>.
    Found 3-bit up counter for signal <COUNT>.
    Summary:
	inferred   1 Counter(s).
Unit <LCD> synthesized.


Synthesizing Unit <BIN_BCD_LCD>.
    Related source file is BIN_BCD_LCD.v.
Unit <BIN_BCD_LCD> synthesized.


Synthesizing Unit <ONE_PULSE_LCD>.
    Related source file is ONE_PULSE_LCD.v.
Unit <ONE_PULSE_LCD> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 7
  1-bit register                   : 4
  4-bit register                   : 3
# Latches                          : 2
  4-bit latch                      : 1
  5-bit latch                      : 1
# Counters                         : 4
  3-bit up counter                 : 2
  8-bit down counter               : 1
  16-bit up counter                : 1
# Adders/Subtractors               : 4
  8-bit subtractor                 : 3
  4-bit subtractor                 : 1
# Comparators                      : 29
  8-bit comparator less            : 29

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Library "D:/Xilinx52/xc9500/data/lib.xst" Consulted
WARNING:Xst:1293 - FF/Latch  <LD_0> is constant in block <LCD>.
WARNING:Xst:1293 - FF/Latch  <LD_1> is constant in block <LCD>.
WARNING:Xst:1293 - FF/Latch  <BB_3> is constant in block <BIN_BCD>.
WARNING:Xst:1293 - FF/Latch  <BB_2> is constant in block <BIN_BCD>.
Library "D:/Xilinx52/data/librtl.xst" Consulted

Optimizing unit <ONE_PULSE_LCD> ...

Optimizing unit <DFF_R> ...

Optimizing unit <TFF> ...

Optimizing unit <DFF_R1> ...

Optimizing unit <P_DETECT> ...

Optimizing unit <LCD> ...

Optimizing unit <BIN_BCD> ...

Optimizing unit <CNT> ...

Optimizing unit <LD_EN_DCNT> ...

Optimizing unit <DELAY> ...

Optimizing unit <BIN_BCD_LCD> ...

Optimizing unit <P_DLY> ...

Optimizing unit <ONE_PULSE> ...

Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".

Release 5.2.03i - ngdbuild F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc ONE_PULSE_LCD.ucf -p xc9500
ONE_PULSE_LCD.ngc ONE_PULSE_LCD.ngd 

Reading NGO file "D:/Xilinx52/Wtest/ONE_PULSE_LCD/ONE_PULSE_LCD.ngc" ...
Reading component libraries for design expansion...
INFO:NgdBuild:782 - output buffer 'LD_4_OBUF' driving design level port 'LD<4>'
   is being pushed into module 'BIN_BCD_LCD/LCD' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'LD_3_OBUF' driving design level port 'LD<3>'
   is being pushed into module 'BIN_BCD_LCD/LCD' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'LD_2_OBUF' driving design level port 'LD<2>'
   is being pushed into module 'BIN_BCD_LCD/LCD' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'P_3_OBUF' driving design level port 'P<3>' is
   being pushed into module 'BIN_BCD_LCD/LCD' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'P_2_OBUF' driving design level port 'P<2>' is
   being pushed into module 'BIN_BCD_LCD/LCD' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'P_1_OBUF' driving design level port 'P<1>' is
   being pushed into module 'BIN_BCD_LCD/LCD' to enable I/O register usage.
INFO:NgdBuild:782 - output buffer 'P_0_OBUF' driving design level port 'P<0>' is
   being pushed into module 'BIN_BCD_LCD/LCD' to enable I/O register usage.

Annotating constraints to design from file "ONE_PULSE_LCD.ucf" ...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:452 - logical net 'BIN_BCD_LCD/BB<2>' has no driver
WARNING:NgdBuild:454 - logical net 'BIN_BCD_LCD/BB<2>' has no load
WARNING:NgdBuild:452 - logical net 'BIN_BCD_LCD/BIN_BCD/N794' has no driver
WARNING:NgdBuild:454 - logical net 'BIN_BCD_LCD/BIN_BCD/N794' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   4

Writing NGD file "ONE_PULSE_LCD.ngd" ...

Writing NGDBUILD log file "ONE_PULSE_LCD.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Fit".

Release 5.2.03i - CPLD Optimizer/Partitioner F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Considering device XC95108-PQ100.
Flattening design..
Multi-level logic optimization...
Timing optimization...............................................................................................................
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 81 equations into 6 function blocks.WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6,
   because too many function block product terms are required. Buffering output
   signal DP<0> to allow all signals assigned to this function block to be
   placed.
.................................................

Design ONE_PULSE_LCD has been optimized and fit into device XC95108-7-PQ100.

Completed process "Fit".


Started process "Generate Timing".

Release 5.2.03i - Timing Report Generator F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Path tracing .....ERROR: TAENGINE failed
Reason: 

Completed process "Generate Timing".


Project Navigator Auto-Make Log File
-------------------------------------


Started process "Generate Programming File".

Release 5.2.03i - Programming File Generator F.31
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------

JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    D:/Xilinx52/verilog/src/iSE/unisim_comp.v
Scanning    ONE_PULSE_LCD.v
Scanning    ONE_PULSE.v
Scanning    BIN_BCD_LCD.v