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WARNING:NgdBuild:454 - logical net 'LCD_DISPLAY/BIN_BCD/N794' has no loadNGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 4Writing NGD file "ONE_PULSE_LCD.ngd" ...Writing NGDBUILD log file "ONE_PULSE_LCD.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2.03i - CPLD Optimizer/Partitioner F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95108-PQ100.Flattening design..Multi-level logic optimization...Timing optimization................................................................................................................Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 81 equations into 6 function blocks..................................................................Design ONE_PULSE_LCD has been optimized and fit into device XC95108-7-PQ100.Completed process "Fit".Started process "Generate Timing".Release 5.2.03i - Timing Report Generator F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Path tracing .....ERROR: TAENGINE failedReason: Completed process "Generate Timing".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 5.2.03i - ngdbuild F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -i -p xc9500 ONE_PULSE_LCD.ngc ONE_PULSE_LCD.ngdReading NGO file "D:/Xilinx52/Wtest/ONE_PULSE_LCD/ONE_PULSE_LCD.ngc" ...Reading component libraries for design expansion...INFO:NgdBuild:782 - output buffer 'LD_4_OBUF' driving design level port 'LD<4>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'LD_3_OBUF' driving design level port 'LD<3>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'LD_2_OBUF' driving design level port 'LD<2>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_3_OBUF' driving design level port 'P<3>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_2_OBUF' driving design level port 'P<2>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_1_OBUF' driving design level port 'P<1>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_0_OBUF' driving design level port 'P<0>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.Checking timing specifications ...Checking expanded design ...WARNING:NgdBuild:452 - logical net 'LCD_DISPLAY/BB<2>' has no driverWARNING:NgdBuild:454 - logical net 'LCD_DISPLAY/BB<2>' has no loadWARNING:NgdBuild:452 - logical net 'LCD_DISPLAY/BIN_BCD/N794' has no driverWARNING:NgdBuild:454 - logical net 'LCD_DISPLAY/BIN_BCD/N794' has no loadNGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 4Writing NGD file "ONE_PULSE_LCD.ngd" ...Writing NGDBUILD log file "ONE_PULSE_LCD.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2.03i - CPLD Optimizer/Partitioner F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95108-PQ100.Flattening design..Multi-level logic optimization...Timing optimization................................................................................................................Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 81 equations into 6 function blocks..................................................................Design ONE_PULSE_LCD has been optimized and fit into device XC95108-7-PQ100.Completed process "Fit".Started process "Generate Timing".Release 5.2.03i - Timing Report Generator F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Path tracing .....ERROR: TAENGINE failedReason: Completed process "Generate Timing".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Release 5.2.03i - Programming File Generator F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Release 5.2.03i - ngdbuild F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc ONE_PULSE_LCD.ucf -p xc9500ONE_PULSE_LCD.ngc ONE_PULSE_LCD.ngd Reading NGO file "D:/Xilinx52/Wtest/ONE_PULSE_LCD/ONE_PULSE_LCD.ngc" ...Reading component libraries for design expansion...INFO:NgdBuild:782 - output buffer 'LD_4_OBUF' driving design level port 'LD<4>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'LD_3_OBUF' driving design level port 'LD<3>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'LD_2_OBUF' driving design level port 'LD<2>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_3_OBUF' driving design level port 'P<3>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_2_OBUF' driving design level port 'P<2>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_1_OBUF' driving design level port 'P<1>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.INFO:NgdBuild:782 - output buffer 'P_0_OBUF' driving design level port 'P<0>' is being pushed into module 'LCD_DISPLAY/LCD' to enable I/O register usage.Annotating constraints to design from file "ONE_PULSE_LCD.ucf" ...Checking timing specifications ...Checking expanded design ...WARNING:NgdBuild:452 - logical net 'LCD_DISPLAY/BB<2>' has no driverWARNING:NgdBuild:454 - logical net 'LCD_DISPLAY/BB<2>' has no loadWARNING:NgdBuild:452 - logical net 'LCD_DISPLAY/BIN_BCD/N794' has no driverWARNING:NgdBuild:454 - logical net 'LCD_DISPLAY/BIN_BCD/N794' has no loadNGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 4Writing NGD file "ONE_PULSE_LCD.ngd" ...Writing NGDBUILD log file "ONE_PULSE_LCD.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 5.2.03i - CPLD Optimizer/Partitioner F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Considering device XC95108-PQ100.Flattening design..Multi-level logic optimization...Timing optimization................................................................................................................Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 81 equations into 6 function blocks.WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6, because too many function block product terms are required. Buffering output signal DP<0> to allow all signals assigned to this function block to be placed..................................................Design ONE_PULSE_LCD has been optimized and fit into device XC95108-7-PQ100.Completed process "Fit".Started process "Generate Timing".Release 5.2.03i - Timing Report Generator F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Path tracing .....ERROR: TAENGINE failedReason: Completed process "Generate Timing".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Generate Programming File".Release 5.2.03i - Programming File Generator F.31Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
JHDPARSE - VHDL/Verilog Parser.
ISE 5.2i Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Scanning D:/Xilinx52/verilog/src/iSE/unisim_comp.v
Scanning ONE_PULSE_LCD.v
Scanning ONE_PULSE.v
Scanning BIN_BCD_LCD.v
Writing ONE_PULSE_LCD.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "ONE_PULSE_LCD.prj"Compiling include file "ONE_PULSE_LCD.v"Compiling include file "ONE_PULSE.v"Module <ONE_PULSE> compiledModule <LD_EN_DCNT> compiledModule <P_DLY> compiledModule <DELAY> compiledModule <P_DETECT> compiledModule <DFF_R1> compiledModule <DFF_R> compiledModule <TFF> compiledCompiling include file "BIN_BCD_LCD.v"Module <BIN_BCD_LCD> compiledModule <CNT> compiledModule <LCD> compiledModule <BIN_BCD> compiledModule <ONE_PULSE_LCD> compiledCompiling include file "D:/Xilinx52/verilog/src/iSE/unisim_comp.v"No errors in compilation=========================================================================* HDL Analysis *=========================================================================Analysis of file <ONE_PULSE_LCD.prj> succeeded. Analyzing module <DFF_R1>.Module <DFF_R1> is correct for synthesis. Analyzing module <DELAY>.Module <DELAY> is correct for synthesis. Analyzing module <TFF>.Module <TFF> is correct for synthesis. Analyzing module <P_DLY>.Module <P_DLY> is correct for synthesis. Analyzing module <LD_EN_DCNT>.Module <LD_EN_DCNT> is correct for synthesis. Analyzing module <DFF_R>.Module <DFF_R> is correct for synthesis. Analyzing module <P_DETECT>.Module <P_DETECT> is correct for synthesis. Analyzing module <ONE_PULSE>.Module <ONE_PULSE> is correct for synthesis. ⌨️ 快捷键说明
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