one_pulse.v

具有LCD显示单元的可编程单脉冲发生器的硬件实现

//********************************************
// 可编程单脉冲发生器 
//*******************************************


module ONE_PULSE ( CLK, RB, DATA_IN, P_PULSE, KEY, LED_OUT);
     input    CLK, RB, KEY;
     input    [7:0] DATA_IN;
     output   P_PULSE;
     output   [7:0] LED_OUT;
     wire     OUT, LOAD, DLY_OUT, EN, CNT_OUT;


     assign  LOAD = ~DLY_OUT;
     assign  EN = OUT;
     assign  P_PULSE = CNT_OUT & OUT;
     assign  LED_OUT = ~DATA_IN;

     P_DLY	  U1 ( CLK, RB, DLY_OUT);                   // 延时模块
     LD_EN_DCNT   U2 ( RB, ~CLK, LOAD, EN, DATA_IN, CNT_OUT);    // 计数模块
     P_DETECT     U3 ( RB, CLK, ~KEY , OUT);                     // 输入检测模块

endmodule

//*****************************************************************************
//********************  计数模块	
module	LD_EN_DCNT  (  RESET_B, CLK, LOAD, EN, IN, CNT_OUT);
     input   RESET_B, CLK, LOAD, EN;
     input   [7:0] IN;
     output  CNT_OUT;
     reg     [7:0] Q;

     always  @( posedge CLK )
        if  ( !RESET_B )
		Q <= 0;
        else if	( LOAD )
		Q <= IN;
	     else if ( EN )
		 if ( Q == 0 )
		    Q <= 0;
		 else 
		    Q <= Q - 1;
	
      assign  CNT_OUT =Q[7]  |   Q[6]  |  Q[5]  |  Q[4]  |  Q[3]  |  Q[2]  |  Q[1]  |  Q[0];
endmodule

//*****************************************************************************
//********************  延时模块
module	P_DLY	( CLK, RB, DLY_OUT);
    input  CLK, RB;
    wire  Q, QB, CNT_CLK;  
    output DLY_OUT;

    assign  CNT_CLK = CLK & Q & QB;

    DFF_R1  U1 ( CLK, Q, RB);
    DELAY   U2 ( RB, CNT_CLK , DLY_OUT);
    TFF     U3 ( DLY_OUT, QB, RB );

endmodule

//********************  DELAY
module	DELAY	( RESET_B, CLK, DIV_CLK );
    input   RESET_B, CLK;
    output  DIV_CLK;
    reg	    [2:0] Q;
	
    always  @( posedge CLK or negedge RESET_B )
	if ( !RESET_B )
	     Q <= 0;
	else if ( Q == 5 )
		Q <= 0;
	     else
		Q <= Q + 1;
	
    assign DIV_CLK = ~(Q[2] & ~Q[1] & Q[0]);
endmodule

//*****************************************************************************
//******************** 输入检测模块
module P_DETECT( RB, CLK, IN, P_Q);
    input  IN, CLK, RB;
    output P_Q;
	
    DFF_R  U1 ( CLK2 , IN & P_QB, P_Q, P_QB, RB);
    TFF     U2 ( P_Q, T_QB, RB);
	
    assign  CLK2 = CLK & T_QB;

endmodule

//******************** DFF_R1
module DFF_R1( CK, Q, RB);
    input  CK, RB;
    output Q;
    reg    Q;
   
    always @( negedge CK or negedge RB ) begin
       if ( RB==0 )
          Q <= 0;
       else
          Q <= 1;
end

endmodule


//******************** DFF_R
module DFF_R( CK, D, Q, QB, RB);
    input  CK, D, RB;
    output Q, QB;
    reg    Q;

    always @( negedge CK or negedge RB ) 
      begin
       if ( RB==0 )
          Q <= 0;
       else
          Q <= D;
      end

   assign QB = ~Q;
endmodule

//******************** TFF
module TFF( T, QB, RB );
    input  T, RB;
    output QB;
    reg    QB;

    always @( posedge T or negedge RB )
      begin
         if ( RB==0 )
            QB <= 1;
         else  
            QB <= ~QB;
      end
endmodule