sinwave.vhd

正弦波信号发生的源码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY sinwave IS
	PORT
	(
		CLK			:	IN 	STD_LOGIC;	                   --//信号源时钟
		DOUT		:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)	--//8位波形数据输出
	);
END;

ARCHITECTURE DACC OF sinwave IS
	COMPONENT drom	                                          --//调用波形数据存储器LPM_ROM文件：drom.vhd
		PORT
		(
			address		:	IN	STD_LOGIC_VECTOR(5 DOWNTO 0);	--//6位地址信号
			clock		:	IN	STD_LOGIC;						--//地址锁存时钟
			q			:	OUT	STD_LOGIC_VECTOR(7 DOWNTO 0)
		);
	END COMPONENT;

		SIGNAL Q1 : STD_LOGIC_VECTOR(5 DOWNTO 0);	--//内部节点作为地址计数器
		SIGNAL newclk: STD_LOGIC;
		SIGNAL clk_cnt:STD_LOGIC_VECTOR(4 DOWNTO 0);
		
	BEGIN
		newclk	<=	clk_cnt(4);		
		---------------------------
		PROCESS (CLK)
		BEGIN
			IF CLK'EVENT AND CLK= '1' THEN
				clk_cnt	<=	clk_cnt+1;
			END IF;
		END PROCESS;
		---------------------------
		PROCESS (newclk)
		BEGIN
			IF newclk'EVENT AND newclk= '1' THEN
				Q1<=Q1+1;
			END IF;
		END PROCESS;

	u1:drom PORT MAP(address=>Q1,clock=>CLK,q=>DOUT);--//例化
END DACC;