uart_exam.vhd

VHDL写的串口

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY uart_exam IS
	--GENERIC
	--(
	--	__parameter_name	: string :=	__default_value;
	--	__parameter_name	: integer:=	__default_value
	--);
	PORT
	(
		clk		: IN	STD_LOGIC;
		--__input_vector_name				: IN	STD_LOGIC_VECTOR(__high DOWNTO __low);
		--__bidir_name, __bidir_name		: INOUT	STD_LOGIC;
		txd	: OUT	STD_LOGIC
	);
END uart_exam;
ARCHITECTURE a OF uart_exam IS
	SIGNAL baud_count : STD_LOGIC_VECTOR(8 DOWNTO 0);
	SIGNAL bit_flag: STD_LOGIC;
	SIGNAL uart_buf : std_logic_vector(7 downto 0):="01100101";
	signal bit_cnt : std_logic_vector(3 downto 0):="0000";
BEGIN
	-- Process Statement (optional)

	-- Concurrent Procedure Call (optional)

	-- Concurrent Signal Assignment (optional)

	-- Conditional Signal Assignment (optional)

	-- Selected Signal Assignment (optional)

	-- Component Instantiation Statement (optional)

	-- Generate Statement (optional)
	uart_buf<="01100101";
PROCESS (clk)
	--VARIABLE __variable_name	:	STD_LOGIC;
	--VARIABLE __variable_name	:	STD_LOGIC;
BEGIN
	-- Signal Assignment Statement (optional)

	-- Variable Assignment Statement (optional)

	-- Procedure Call Statement (optional)

	-- If Statement (optional)

	-- Case Statement (optional)

	-- Loop Statement (optional)
	IF (clk'event and clk='1' and clk'last_value='0') THEN
    IF (baud_count<"101011010") THEN
      bit_flag<='0';
      baud_count<=baud_count +'1'; 
ELSE
      baud_count<="000000000";
	  bit_flag<='1';
END IF;

END IF;

END PROCESS ;

PROCESS (bit_flag)
	--VARIABLE __variable_name	:	STD_LOGIC;
	--VARIABLE __variable_name	:	STD_LOGIC;
BEGIN
	-- Signal Assignment Statement (optional)

	-- Variable Assignment Statement (optional)

	-- Procedure Call Statement (optional)

	-- If Statement (optional)

	-- Case Statement (optional)

	-- Loop Statement (optional)
	IF (bit_flag'event and bit_flag='1' and bit_flag'last_value='0') THEN
	
IF (bit_cnt<"1001") THEN
	bit_cnt<=bit_cnt+'1';
	
ELSE
	bit_cnt<="0000";
END IF;

END IF;

END PROCESS ;

PROCESS (bit_cnt,uart_buf)
	--VARIABLE __variable_name	:	STD_LOGIC;
	--VARIABLE __variable_name	:	STD_LOGIC;
BEGIN
	-- Signal Assignment Statement (optional)

	-- Variable Assignment Statement (optional)

	-- Procedure Call Statement (optional)

	-- If Statement (optional)

	-- Case Statement (optional)

	-- Loop Statement (optional)
	case(bit_cnt) is
	when "0000" =>txd<='0';
	when "0001" =>txd<=uart_buf(0);
	when "0010" =>txd<=uart_buf(1);
	when "0011" =>txd<=uart_buf(2);
	when "0100" =>txd<=uart_buf(3);
	when "0101" =>txd<=uart_buf(4);
	when "0110" =>txd<=uart_buf(5);
	when "0111" =>txd<=uart_buf(6);
	when "1000" =>txd<=uart_buf(7);
	when "1001" =>txd<='1';
	when others =>txd <='1';
	end case;
END PROCESS ;

END a;