div16_8.vhd

用FPGA实现模糊控制器 部分用VHDL语言编写的源程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY div16_8 IS
	PORT
	(
		numerator		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		denominator		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
		remainder		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END div16_8;


ARCHITECTURE SYN OF div16_8 IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (15 DOWNTO 0);



	COMPONENT divide
	GENERIC (
		width_n		: NATURAL;
		width_d		: NATURAL;
		width_q		: NATURAL;
		width_r		: NATURAL;
		width_d_min		: NATURAL;
		lpm_pipeline		: NATURAL;
		pipeline_delay		: NATURAL
	);
	PORT (
			numerator	: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
			remainder	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
			denominator	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			quotient	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	remainder    <= sub_wire0(7 DOWNTO 0);
	quotient    <= sub_wire1(15 DOWNTO 0);

	divide_component : divide
	GENERIC MAP (
		WIDTH_N => 16,
		WIDTH_D => 8,
		WIDTH_Q => 16,
		WIDTH_R => 8,
		WIDTH_D_MIN => 1,
		LPM_PIPELINE => 0,
		PIPELINE_DELAY => 0
	)
	PORT MAP (
		numerator => numerator,
		denominator => denominator,
		remainder => sub_wire0,
		quotient => sub_wire1
	);



END SYN;