clr_m.vhd

用FPGA实现的模糊控制器 部分用VHDL编写的源程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CLR_M IS
  PORT (
        X_clr:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
        START:IN STD_LOGIC;
        CLK:IN STD_LOGIC;
        clr_INDEX1:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
        clr_INDEX2:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
        a1_clr:out std_LOGIC_VECTOR(7 DOWNTO 0);
        a2_clr:out std_LOGIC_VECTOR(7 DOWNTO 0)
        );
END ENTITY CLR_M;
ARCHITECTURE ART OF CLR_M IS
  SIGNAL IND_REG1:STD_LOGIC_VECTOR(2 DOWNTO 0);
  SIGNAL IND_REG2:STD_LOGIC_VECTOR(2 DOWNTO 0);
  SIGNAL S1:STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL Q1:STD_LOGIC_VECTOR(7 DOWNTO 0);
  SIGNAL S2:STD_LOGIC_VECTOR(15 DOWNTO 0);
  SIGNAL Q2:STD_LOGIC_VECTOR(7 DOWNTO 0);
  CONSTANT V1:STD_LOGIC_VECTOR(7 DOWNTO 0):="00011010";
  CONSTANT V2:STD_LOGIC_VECTOR(7 DOWNTO 0):="00110011";
  CONSTANT V3:STD_LOGIC_VECTOR(7 DOWNTO 0):="01001100";
  CONSTANT V4:STD_LOGIC_VECTOR(7 DOWNTO 0):="10000000";
  COMPONENT DIV16_8 IS
	PORT
	(
		numerator		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		denominator		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
		remainder		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
  END COMPONENT DIV16_8;

    BEGIN
     U1:DIV16_8 PORT MAP(S1,q1,a1_clr);
     U2:DIV16_8 PORT MAP(s2,q2,a2_clr);
   
   PROCESS(CLK)
      BEGIN
    IF RISING_EDGE(CLK) THEN
      IF START='1' THEN
        IF X_clr<=V1 THEN
          IND_REG1<="000";
          IND_REG2<="000";
          S1(15 DOWNTO 8)<="00000000";
          S1(7 DOWNTO 0)<="11111111";    
          Q1<="00000001";
          S2(15 DOWNTO 8)<="00000000";
          S2(7 DOWNTO 0)<="11111111";    
          Q2<="00000001";
        ELSIF X_clr>V1 AND X_clr<V2 THEN
          IND_REG1<="000";
          IND_REG2<="001";
          S1(15 DOWNTO 8)<=V2-X_clr;
          S1(7 DOWNTO 0)<="00000000";    
          Q1<=V2-V1;
          S2(15 DOWNTO 8)<=X_clr-V1;
          S2(7 DOWNTO 0)<="00000000";    
          Q2<=V2-V1;
        ELSIF X_clr=V2 THEN
          IND_REG1<="000";
          IND_REG2<="000";
          S1(15 DOWNTO 8)<="00000000";
          S1(7 DOWNTO 0)<="11111111";    
          Q1<="00000001";
          S2(15 DOWNTO 8)<="00000000";
          S2(7 DOWNTO 0)<="11111111";    
          Q2<="00000001";
        ELSIF X_clr>V2 AND X_clr<V3 THEN
          IND_REG1<="001";
          IND_REG2<="010";
          S1(15 DOWNTO 8)<=V3-X_clr;
          S1(7 DOWNTO 0)<="00000000";    
          Q1<=V3-V2;
          S2(15 DOWNTO 8)<=X_clr-V2;
          S2(7 DOWNTO 0)<="00000000";    
          Q2<=V3-V2;
        ELSIF X_clr=V3 THEN
          IND_REG1<="010";
          IND_REG2<="010";
          S1(15 DOWNTO 8)<="00000000";
          S1(7 DOWNTO 0)<="11111111";    
          Q1<="00000001";
          S2(15 DOWNTO 8)<="00000000";
          S2(7 DOWNTO 0)<="11111111";    
          Q2<="00000001";
        ELSIF X_clr>V3 AND X_clr<V4 THEN
          IND_REG1<="010";
          IND_REG2<="011";
          S1(15 DOWNTO 8)<=V4-X_clr;
          S1(7 DOWNTO 0)<="00000000";    
          Q1<=V4-V3;
          S2(15 DOWNTO 8)<=X_clr-V3;
          S2(7 DOWNTO 0)<="00000000";    
          Q2<=V4-V3;
        ELSIF X_clr>=V4 THEN
          IND_REG1<="011";
          IND_REG2<="011";
          S1(15 DOWNTO 8)<="00000000";
          S1(7 DOWNTO 0)<="11111111";    
          Q1<="00000001";
          S2(15 DOWNTO 8)<="00000000";
          S2(7 DOWNTO 0)<="11111111";    
          Q2<="00000001";
        END IF;
      END IF;
    END IF;
  END PROCESS;
   clr_INDEX1<=IND_REG1;
   clr_INDEX2<=IND_REG2;
   
END ARCHITECTURE ART;