prev_cmp_dds.fit.qmsg

来自「DDs直接数字频率合成器的源代码」· QMSG 代码 · 共 52 行 · 第 1/4 页

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.806 ns register register " "Info: Estimated most critical path is register to register delay of 2.806 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\] 1 REG LAB_X18_Y8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X18_Y8; Fanout = 3; REG Node = 'lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1_0\[1\]\|a_csnbuffer:result_node\|sout_node\[3\]'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.575 ns) 1.274 ns AddrLock:inst3\|ADDRLOCK\[19\]~74COUT1_109 2 COMB LAB_X17_Y8 2 " "Info: 2: + IC(0.699 ns) + CELL(0.575 ns) = 1.274 ns; Loc. = LAB_X17_Y8; Fanout = 2; COMB Node = 'AddrLock:inst3\|ADDRLOCK\[19\]~74COUT1_109'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] AddrLock:inst3|ADDRLOCK[19]~74COUT1_109 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.354 ns AddrLock:inst3\|ADDRLOCK\[20\]~72COUT1_111 3 COMB LAB_X17_Y8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.354 ns; Loc. = LAB_X17_Y8; Fanout = 2; COMB Node = 'AddrLock:inst3\|ADDRLOCK\[20\]~72COUT1_111'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { AddrLock:inst3|ADDRLOCK[19]~74COUT1_109 AddrLock:inst3|ADDRLOCK[20]~72COUT1_111 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.434 ns AddrLock:inst3\|ADDRLOCK\[21\]~70COUT1_113 4 COMB LAB_X17_Y8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.434 ns; Loc. = LAB_X17_Y8; Fanout = 2; COMB Node = 'AddrLock:inst3\|ADDRLOCK\[21\]~70COUT1_113'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { AddrLock:inst3|ADDRLOCK[20]~72COUT1_111 AddrLock:inst3|ADDRLOCK[21]~70COUT1_113 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.514 ns AddrLock:inst3\|ADDRLOCK\[22\]~68COUT1_115 5 COMB LAB_X17_Y8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.514 ns; Loc. = LAB_X17_Y8; Fanout = 2; COMB Node = 'AddrLock:inst3\|ADDRLOCK\[22\]~68COUT1_115'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { AddrLock:inst3|ADDRLOCK[21]~70COUT1_113 AddrLock:inst3|ADDRLOCK[22]~68COUT1_115 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.772 ns AddrLock:inst3\|ADDROUT\[0\]~46 6 COMB LAB_X17_Y8 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.772 ns; Loc. = LAB_X17_Y8; Fanout = 6; COMB Node = 'AddrLock:inst3\|ADDROUT\[0\]~46'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.258 ns" { AddrLock:inst3|ADDRLOCK[22]~68COUT1_115 AddrLock:inst3|ADDROUT[0]~46 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.908 ns AddrLock:inst3\|ADDROUT\[5\]~56 7 COMB LAB_X17_Y7 3 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.908 ns; Loc. = LAB_X17_Y7; Fanout = 3; COMB Node = 'AddrLock:inst3\|ADDROUT\[5\]~56'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { AddrLock:inst3|ADDROUT[0]~46 AddrLock:inst3|ADDROUT[5]~56 } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 2.806 ns AddrLock:inst3\|ADDROUT\[6\] 8 REG LAB_X17_Y7 13 " "Info: 8: + IC(0.000 ns) + CELL(0.898 ns) = 2.806 ns; Loc. = LAB_X17_Y7; Fanout = 13; REG Node = 'AddrLock:inst3\|ADDROUT\[6\]'" {  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { AddrLock:inst3|ADDROUT[5]~56 AddrLock:inst3|ADDROUT[6] } "NODE_NAME" } } { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.107 ns ( 75.09 % ) " "Info: Total cell delay = 2.107 ns ( 75.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.699 ns ( 24.91 % ) " "Info: Total interconnect delay = 0.699 ns ( 24.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "2.806 ns" { lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[3] AddrLock:inst3|ADDRLOCK[19]~74COUT1_109 AddrLock:inst3|ADDRLOCK[20]~72COUT1_111 AddrLock:inst3|ADDRLOCK[21]~70COUT1_113 AddrLock:inst3|ADDRLOCK[22]~68COUT1_115 AddrLock:inst3|ADDROUT[0]~46 AddrLock:inst3|ADDROUT[5]~56 AddrLock:inst3|ADDROUT[6] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Info: Average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "5 X14_Y0 X27_Y14 " "Info: Peak interconnect usage is 5% of the available device resources in the region that extends from location X14_Y0 to location X27_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:06 " "Info: Fitter routing operations ending: elapsed time is 00:00:06" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: Following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "q_out\[13\] GND " "Info: Pin q_out\[13\] has GND driving its datain port" {  } { { "d:/altera/quartus72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus72/quartus/bin/pin_planner.ppl" { q_out[13] } } } { "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q_out\[13\]" } } } } { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { { 112 520 696 128 "q_out\[13..0\]" "" } { 176 696 757 192 "q_out\[9..0\]" "" } } } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[13] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[13] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "q_out\[12\] GND " "Info: Pin q_out\[12\] has GND driving its datain port" {  } { { "d:/altera/quartus72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus72/quartus/bin/pin_planner.ppl" { q_out[12] } } } { "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q_out\[12\]" } } } } { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { { 112 520 696 128 "q_out\[13..0\]" "" } { 176 696 757 192 "q_out\[9..0\]" "" } } } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[12] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[12] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "q_out\[11\] GND " "Info: Pin q_out\[11\] has GND driving its datain port" {  } { { "d:/altera/quartus72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus72/quartus/bin/pin_planner.ppl" { q_out[11] } } } { "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q_out\[11\]" } } } } { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { { 112 520 696 128 "q_out\[13..0\]" "" } { 176 696 757 192 "q_out\[9..0\]" "" } } } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[11] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[11] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "q_out\[10\] GND " "Info: Pin q_out\[10\] has GND driving its datain port" {  } { { "d:/altera/quartus72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/quartus72/quartus/bin/pin_planner.ppl" { q_out[10] } } } { "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus72/quartus/bin/Assignment Editor.qase" 1 { { 0 "q_out\[10\]" } } } } { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { { 112 520 696 128 "q_out\[13..0\]" "" } { 176 696 757 192 "q_out\[9..0\]" "" } } } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[10] } "NODE_NAME" } } { "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus72/quartus/bin/TimingClosureFloorplan.fld" "" "" { q_out[10] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/yezi/design/dds/dds.fit.smsg " "Info: Generated suppressed messages file E:/yezi/design/dds/dds.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "175 " "Info: Allocated 175 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 04 20:53:49 2008 " "Info: Processing ended: Tue Mar 04 20:53:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:38 " "Info: Elapsed time: 00:00:38" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}