dds.map.qmsg

来自「DDs直接数字频率合成器的源代码」· QMSG 代码 · 共 67 行 · 第 1/5 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_pharse.vhd" "lpm_add_sub_component" { Text "E:/ttqing/dds/lpm_add_pharse.vhd" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "lpm_add_pharse.vhd" "" { Text "E:/ttqing/dds/lpm_add_pharse.vhd" 75 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_omg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_omg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_omg " "Info: Found entity 1: add_sub_omg" {  } { { "db/add_sub_omg.tdf" "" { Text "E:/ttqing/dds/db/add_sub_omg.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_omg lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|add_sub_omg:auto_generated " "Info: Elaborating entity \"add_sub_omg\" for hierarchy \"lpm_add_pharse:inst1\|lpm_add_sub:lpm_add_sub_component\|add_sub_omg:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 117 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "DPLL.vhd 2 1 " "Warning: Using design file DPLL.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dpll-SYN " "Info: Found design unit 1: dpll-SYN" {  } { { "DPLL.vhd" "" { Text "E:/ttqing/dds/DPLL.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DPLL " "Info: Found entity 1: DPLL" {  } { { "DPLL.vhd" "" { Text "E:/ttqing/dds/DPLL.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DPLL DPLL:inst4 " "Info: Elaborating entity \"DPLL\" for hierarchy \"DPLL:inst4\"" {  } { { "dds.bdf" "inst4" { Schematic "E:/ttqing/dds/dds.bdf" { { 448 32 288 608 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll DPLL:inst4\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"DPLL:inst4\|altpll:altpll_component\"" {  } { { "DPLL.vhd" "altpll_component" { Text "E:/ttqing/dds/DPLL.vhd" 92 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "DPLL:inst4\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"DPLL:inst4\|altpll:altpll_component\"" {  } { { "DPLL.vhd" "" { Text "E:/ttqing/dds/DPLL.vhd" 92 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_constant0.vhd 4 2 " "Warning: Using design file lpm_constant0.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_constant0_lpm_constant_ama-RTL " "Info: Found design unit 1: lpm_constant0_lpm_constant_ama-RTL" {  } { { "lpm_constant0.vhd" "" { Text "E:/ttqing/dds/lpm_constant0.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 lpm_constant0-RTL " "Info: Found design unit 2: lpm_constant0-RTL" {  } { { "lpm_constant0.vhd" "" { Text "E:/ttqing/dds/lpm_constant0.vhd" 105 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_constant0_lpm_constant_ama " "Info: Found entity 1: lpm_constant0_lpm_constant_ama" {  } { { "lpm_constant0.vhd" "" { Text "E:/ttqing/dds/lpm_constant0.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 lpm_constant0 " "Info: Found entity 2: lpm_constant0" {  } { { "lpm_constant0.vhd" "" { Text "E:/ttqing/dds/lpm_constant0.vhd" 97 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant0 lpm_constant0:inst2 " "Info: Elaborating entity \"lpm_constant0\" for hierarchy \"lpm_constant0:inst2\"" {  } { { "dds.bdf" "inst2" { Schematic "E:/ttqing/dds/dds.bdf" { { 144 -160 -64 192 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_constant0_lpm_constant_ama lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component " "Info: Elaborating entity \"lpm_constant0_lpm_constant_ama\" for hierarchy \"lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component\"" {  } { { "lpm_constant0.vhd" "lpm_constant0_lpm_constant_ama_component" { Text "E:/ttqing/dds/lpm_constant0.vhd" 122 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component\|sld_mod_ram_rom:mgl_prim1 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component\|sld_mod_ram_rom:mgl_prim1\"" {  } { { "lpm_constant0.vhd" "mgl_prim1" { Text "E:/ttqing/dds/lpm_constant0.vhd" 75 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component\|sld_mod_ram_rom:mgl_prim1 " "Info: Elaborated megafunction instantiation \"lpm_constant0:inst2\|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component\|sld_mod_ram_rom:mgl_prim1\"" {  } { { "lpm_constant0.vhd" "" { Text "E:/ttqing/dds/lpm_constant0.vhd" 75 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}