dds.map.qmsg

来自「DDs直接数字频率合成器的源代码」· QMSG 代码 · 共 67 行 · 第 1/5 页

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ra51 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated " "Info: Elaborating entity \"altsyncram_ra51\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus60/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_47j2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_47j2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_47j2 " "Info: Found entity 1: altsyncram_47j2" {  } { { "db/altsyncram_47j2.tdf" "" { Text "E:/ttqing/dds/db/altsyncram_47j2.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_47j2 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|altsyncram_47j2:altsyncram1 " "Info: Elaborating entity \"altsyncram_47j2\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|altsyncram_47j2:altsyncram1\"" {  } { { "db/altsyncram_ra51.tdf" "altsyncram1" { Text "E:/ttqing/dds/db/altsyncram_ra51.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_ra51.tdf" "mgl_prim2" { Text "E:/ttqing/dds/db/altsyncram_ra51.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_ra51.tdf" "" { Text "E:/ttqing/dds/db/altsyncram_ra51.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\", which is child of megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 635 -1 0 } } { "db/altsyncram_ra51.tdf" "" { Text "E:/ttqing/dds/db/altsyncram_ra51.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_ra51:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 0000000000 " "Info: Parameter \"CVALUE\" = \"0000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1650614784 " "Info: Parameter \"NODE_NAME\" = \"1650614784\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 512 " "Info: Parameter \"NUMWORDS\" = \"512\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 4 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 10 " "Info: Parameter \"WIDTH_WORD\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 9 " "Info: Parameter \"WIDTHAD\" = \"9\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "db/altsyncram_ra51.tdf" "" { Text "E:/ttqing/dds/db/altsyncram_ra51.tdf" 35 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AddrLock AddrLock:inst3 " "Info: Elaborating entity \"AddrLock\" for hierarchy \"AddrLock:inst3\"" {  } { { "dds.bdf" "inst3" { Schematic "E:/ttqing/dds/dds.bdf" { { 152 248 472 248 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_add_pharse.vhd 2 1 " "Warning: Using design file lpm_add_pharse.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_add_pharse-SYN " "Info: Found design unit 1: lpm_add_pharse-SYN" {  } { { "lpm_add_pharse.vhd" "" { Text "E:/ttqing/dds/lpm_add_pharse.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_pharse " "Info: Found entity 1: lpm_add_pharse" {  } { { "lpm_add_pharse.vhd" "" { Text "E:/ttqing/dds/lpm_add_pharse.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_pharse lpm_add_pharse:inst1 " "Info: Elaborating entity \"lpm_add_pharse\" for hierarchy \"lpm_add_pharse:inst1\"" {  } { { "dds.bdf" "inst1" { Schematic "E:/ttqing/dds/dds.bdf" { { 128 24 184 224 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}