prev_cmp_dds.map.qmsg

DDs直接数字频率合成器的源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version " "Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 04 20:52:22 2008 " "Info: Processing started: Tue Mar 04 20:52:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dds -c dds " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AddrLock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file AddrLock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AddrLock-RTL " "Info: Found design unit 1: AddrLock-RTL" {  } { { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 AddrLock " "Info: Found entity 1: AddrLock" {  } { { "AddrLock.vhd" "" { Text "E:/yezi/design/dds/AddrLock.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dds.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dds " "Info: Found entity 1: dds" {  } { { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/design/dds/nco_st.v " "Warning: Can't analyze file -- file D:/design/dds/nco_st.v is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/design/dds/nco.vhd " "Warning: Can't analyze file -- file D:/design/dds/nco.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dds " "Info: Elaborating entity \"dds\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "dds " "Warning: Processing legacy GDF or BDF entity \"dds\" with Max+Plus II bus and instance naming rules" {  } { { "dds.bdf" "" { Schematic "E:/yezi/design/dds/dds.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.vhd 2 1 " "Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom0-SYN " "Info: Found design unit 1: lpm_rom0-SYN" {  } { { "lpm_rom0.vhd" "" { Text "E:/yezi/design/dds/lpm_rom0.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.vhd" "" { Text "E:/yezi/design/dds/lpm_rom0.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst\"" {  } { { "dds.bdf" "inst" { Schematic "E:/yezi/design/dds/dds.bdf" { { 152 536 696 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus72/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus72/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.vhd" "altsyncram_component" { Text "E:/yezi/design/dds/lpm_rom0.vhd" 80 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.vhd" "" { Text "E:/yezi/design/dds/lpm_rom0.vhd" 80 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_9d31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_9d31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_9d31 " "Info: Found entity 1: altsyncram_9d31" {  } { { "db/altsyncram_9d31.tdf" "" { Text "E:/yezi/design/dds/db/altsyncram_9d31.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_9d31 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_9d31:auto_generated " "Info: Elaborating entity \"altsyncram_9d31\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_9d31:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/altera/quartus72/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WMIO_MIO_MIF_DATA_TRUNCATION_HEAD" "E:/yezi/design/dds/sin_talbe.mif " "Warning: Width of data items in E:/yezi/design/dds/sin_talbe.mif is greater than the memory width. Truncating data items to fit in memory." {  } { { "E:/yezi/design/dds/sin_talbe.mif" "" { Text "E:/yezi/design/dds/sin_talbe.mif" 23 -1 0 } }  } 0 0 "Width of data items in %1!s! is greater than the memory width. Truncating data items to fit in memory." 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AddrLock AddrLock:inst3 " "Info: Elaborating entity \"AddrLock\" for hierarchy \"AddrLock:inst3\"" {  } { { "dds.bdf" "inst3" { Schematic "E:/yezi/design/dds/dds.bdf" { { 152 248 472 248 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}