dds.fit.eqn

DDs直接数字频率合成器的源代码

H1L13 = AMPP_FUNCTION(WB1_dffe1a[0], L3_WORD_SR[0], H1_HUB_BYPASS_REG);


--H1L14 is sld_hub:sld_hub_inst|hub_tdo~812 at LC_X29_Y14_N8
--operation mode is normal

H1L14 = AMPP_FUNCTION(H1L13, TB9_Q[0], H1L12, RB1L72);


--B1_bypass_reg_out is sld_signaltap:auto_signaltap_0|bypass_reg_out at LC_X27_Y14_N7
--operation mode is normal

B1_bypass_reg_out = AMPP_FUNCTION(A1L5, B1_bypass_reg_out, H1_jtag_debug_mode, altera_internal_jtag, H1L31, !B1_reset_all);


--TB4_Q[5] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[5] at LC_X29_Y11_N1
--operation mode is normal

TB4_Q[5] = AMPP_FUNCTION(A1L5, TB3_Q[5], TB6_Q[5], TB2_Q[0], H1_CLRN_SIGNAL, H1L23);


--TB4_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[3] at LC_X29_Y11_N3
--operation mode is normal

TB4_Q[3] = AMPP_FUNCTION(A1L5, TB3_Q[3], TB6_Q[3], TB2_Q[0], H1_CLRN_SIGNAL, H1L23);


--TB4_Q[4] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[4] at LC_X29_Y11_N0
--operation mode is normal

TB4_Q[4] = AMPP_FUNCTION(A1L5, TB3_Q[4], TB6_Q[4], TB2_Q[0], H1_CLRN_SIGNAL, H1L23);


--H1L15 is sld_hub:sld_hub_inst|hub_tdo~813 at LC_X29_Y14_N0
--operation mode is normal

H1L15 = AMPP_FUNCTION(TB4_Q[4], TB4_Q[5], B1_bypass_reg_out, TB4_Q[3]);


--L2_WORD_SR[0] is sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] at LC_X29_Y15_N4
--operation mode is normal

L2_WORD_SR[0] = AMPP_FUNCTION(A1L5, L2_WORD_SR[1], VB1_state[4], L3_clear_signal, L2L16, VCC, L2L15);


--H1L16 is sld_hub:sld_hub_inst|hub_tdo~814 at LC_X29_Y14_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

H1L16 = AMPP_FUNCTION(TB4_Q[3], L2_WORD_SR[0], TB4_Q[5]);

--Q1_dffs[0] is sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize|dffs[0] at LC_X29_Y14_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q1_dffs[0] = AMPP_FUNCTION(A1L5, Q1_dffs[1], !B1_reset_all, GND, M1_trigger_setup_ena);


--Q4_dffs[0] is sld_signaltap:auto_signaltap_0|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out|dffs[0] at LC_X31_Y15_N5
--operation mode is normal

Q4_dffs[0] = AMPP_FUNCTION(A1L5, B1L28, N1_is_max_write_address_ff, Q4_dffs[1], !B1_reset_all);


--H1L17 is sld_hub:sld_hub_inst|hub_tdo~815 at LC_X29_Y14_N3
--operation mode is normal

H1L17 = AMPP_FUNCTION(Q4_dffs[0], H1L15, H1L16, TB4_Q[4]);


--TB8_Q[1] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1] at LC_X28_Y14_N3
--operation mode is normal

TB8_Q[1] = AMPP_FUNCTION(A1L5, altera_internal_jtag, TB3_Q[8], H1_CLRN_SIGNAL, H1L20);


--H1L18 is sld_hub:sld_hub_inst|hub_tdo~816 at LC_X28_Y14_N7
--operation mode is normal

H1L18 = AMPP_FUNCTION(VB1_state[3], VB1_state[4], H1_jtag_debug_mode_usr1, TB8_Q[1]);


--VB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] at LC_X26_Y12_N6
--operation mode is normal

VB1_state[8] = AMPP_FUNCTION(A1L5, VB1_state[5], VB1_state[7], VCC, !A1L7);


--SB1__clk0 is DPLL:inst4|altpll:altpll_component|_clk0 at PLL_1
SB1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--RB1_constant_update_reg[23] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[23] at LC_X37_Y11_N4
--operation mode is normal

RB1_constant_update_reg[23] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[23], VCC, RB1L73);


--PB8_sout_node[6] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6] at LC_X38_Y12_N8
--operation mode is arithmetic

PB8_sout_node[6]_carry_eqn = (!PB8L9 & PB8L17) # (PB8L9 & PB8L18);
PB8_sout_node[6]_lut_out = F1_ADDRLOCK[22] $ RB1_constant_update_reg[22] $ !PB8_sout_node[6]_carry_eqn;
PB8_sout_node[6] = DFFEAS(PB8_sout_node[6]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L20 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~149 at LC_X38_Y12_N8
--operation mode is arithmetic

PB8L20_cout_0 = F1_ADDRLOCK[22] & (RB1_constant_update_reg[22] # !PB8L17) # !F1_ADDRLOCK[22] & RB1_constant_update_reg[22] & !PB8L17;
PB8L20 = CARRY(PB8L20_cout_0);

--PB8L21 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[6]~149COUT1_200 at LC_X38_Y12_N8
--operation mode is arithmetic

PB8L21_cout_1 = F1_ADDRLOCK[22] & (RB1_constant_update_reg[22] # !PB8L18) # !F1_ADDRLOCK[22] & RB1_constant_update_reg[22] & !PB8L18;
PB8L21 = CARRY(PB8L21_cout_1);


--F1_ADDRLOCK[21] is AddrLock:inst3|ADDRLOCK[21] at LC_X39_Y12_N7
--operation mode is arithmetic

F1_ADDRLOCK[21]_carry_eqn = (!F1L25 & F1L30) # (F1L25 & F1L31);
F1_ADDRLOCK[21]_lut_out = PB8_sout_node[5] $ F1_ADDRLOCK[21]_carry_eqn;
F1_ADDRLOCK[21] = DFFEAS(F1_ADDRLOCK[21]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L33 is AddrLock:inst3|ADDRLOCK[21]~175 at LC_X39_Y12_N7
--operation mode is arithmetic

F1L33_cout_0 = !F1L30 # !PB8_sout_node[5];
F1L33 = CARRY(F1L33_cout_0);

--F1L34 is AddrLock:inst3|ADDRLOCK[21]~175COUT1_236 at LC_X39_Y12_N7
--operation mode is arithmetic

F1L34_cout_1 = !F1L31 # !PB8_sout_node[5];
F1L34 = CARRY(F1L34_cout_1);


--RB1_constant_update_reg[24] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[24] at LC_X37_Y11_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_constant_update_reg[24] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[24], VCC, GND, RB1L73);


--RB1_constant_update_reg[25] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[25] at LC_X37_Y11_N7
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_constant_update_reg[25] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[25], VCC, GND, RB1L73);


--RB1_constant_update_reg[26] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[26] at LC_X38_Y11_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_constant_update_reg[26] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[26], VCC, GND, RB1L73);


--RB1_constant_update_reg[27] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[27] at LC_X38_Y11_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_constant_update_reg[27] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[27], VCC, GND, RB1L73);


--RB1_constant_update_reg[28] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[28] at LC_X36_Y11_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

RB1_constant_update_reg[28] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[28], VCC, GND, RB1L73);


--RB1_constant_update_reg[29] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[29] at LC_X36_Y11_N5
--operation mode is normal

RB1_constant_update_reg[29] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[29], VCC, RB1L73);


--RB1_constant_update_reg[30] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[30] at LC_X36_Y11_N4
--operation mode is normal

RB1_constant_update_reg[30] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[30], VCC, RB1L73);


--RB1_constant_update_reg[31] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_update_reg[31] at LC_X36_Y11_N8
--operation mode is normal

RB1_constant_update_reg[31] = AMPP_FUNCTION(A1L5, RB1_constant_shift_reg[31], VCC, RB1L73);


--VB1_state[7] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[7] at LC_X27_Y12_N8
--operation mode is normal

VB1_state[7] = AMPP_FUNCTION(A1L5, VB1_state[6], A1L7, VCC);


--VB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] at LC_X26_Y12_N8
--operation mode is normal

VB1_state[2] = AMPP_FUNCTION(A1L5, VB1_state[8], VB1_state[1], VB1_state[15], VCC, !A1L7);


--Q5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] at LC_X25_Y13_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[1] = AMPP_FUNCTION(A1L5, Q5_dffs[2], VB1_state[0], GND, VB1_state[11]);


--Q5_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] at LC_X25_Y13_N3
--operation mode is normal

Q5_dffs[8] = AMPP_FUNCTION(A1L5, Q5_dffs[9], VB1_state[0], VB1_state[11]);


--Q5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] at LC_X25_Y13_N7
--operation mode is normal

Q5_dffs[7] = AMPP_FUNCTION(A1L5, Q5_dffs[8], VB1_state[0], VB1_state[11]);


--Q5_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] at LC_X25_Y13_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[6] = AMPP_FUNCTION(A1L5, Q5_dffs[7], VB1_state[0], GND, VB1_state[11]);


--A1L30 is rtl~93 at LC_X25_Y13_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[9]_qfbk = Q5_dffs[9];
A1L30 = !Q5_dffs[7] & !Q5_dffs[6] & !Q5_dffs[9]_qfbk & !Q5_dffs[8];

--Q5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] at LC_X25_Y13_N1
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, VB1_state[0], GND, VB1_state[11]);


--Q5_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2] at LC_X25_Y13_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[2] = AMPP_FUNCTION(A1L5, Q5_dffs[3], VB1_state[0], GND, VB1_state[11]);


--Q5_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5] at LC_X25_Y13_N6
--operation mode is normal

Q5_dffs[5] = AMPP_FUNCTION(A1L5, Q5_dffs[6], VB1_state[0], VB1_state[11]);


--Q5_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4] at LC_X25_Y13_N4
--operation mode is normal

Q5_dffs[4] = AMPP_FUNCTION(A1L5, Q5_dffs[5], VB1_state[0], VB1_state[11]);


--A1L31 is rtl~94 at LC_X25_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[3]_qfbk = Q5_dffs[3];
A1L31 = !Q5_dffs[5] & !Q5_dffs[4] & Q5_dffs[3]_qfbk & Q5_dffs[2];

--Q5_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3] at LC_X25_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[3] = AMPP_FUNCTION(A1L5, Q5_dffs[4], VB1_state[0], GND, VB1_state[11]);


--Q5_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0] at LC_X25_Y13_N0
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[0] = AMPP_FUNCTION(A1L5, Q5_dffs[1], VB1_state[0], GND, VB1_state[11]);


--VB1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] at LC_X8_Y13_N2
--operation mode is normal

VB1_state[0] = AMPP_FUNCTION(A1L5, VB1_state[0], VB1L19, VB1_state[9], A1L7, VCC);


--VB1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] at LC_X26_Y12_N2
--operation mode is normal