dds.fit.eqn

DDs直接数字频率合成器的源代码

F1_ADDRLOCK[22]_carry_eqn = (!F1L25 & F1L33) # (F1L25 & F1L34);
F1_ADDRLOCK[22]_lut_out = PB8_sout_node[6] $ (!F1_ADDRLOCK[22]_carry_eqn);
F1_ADDRLOCK[22] = DFFEAS(F1_ADDRLOCK[22]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L36 is AddrLock:inst3|ADDRLOCK[22]~171 at LC_X39_Y12_N8
--operation mode is arithmetic

F1L36_cout_0 = PB8_sout_node[6] & (!F1L33);
F1L36 = CARRY(F1L36_cout_0);

--F1L37 is AddrLock:inst3|ADDRLOCK[22]~171COUT1_238 at LC_X39_Y12_N8
--operation mode is arithmetic

F1L37_cout_1 = PB8_sout_node[6] & (!F1L34);
F1L37 = CARRY(F1L37_cout_1);


--PB8_sout_node[8] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[8] at LC_X38_Y11_N0
--operation mode is arithmetic

PB8_sout_node[8]_carry_eqn = PB8L23;
PB8_sout_node[8]_lut_out = RB1_constant_update_reg[24] $ F1_ADDRLOCK[24] $ !PB8_sout_node[8]_carry_eqn;
PB8_sout_node[8] = DFFEAS(PB8_sout_node[8]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L25 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[8]~117 at LC_X38_Y11_N0
--operation mode is arithmetic

PB8L25_cout_0 = RB1_constant_update_reg[24] & (F1_ADDRLOCK[24] # !PB8L23) # !RB1_constant_update_reg[24] & F1_ADDRLOCK[24] & !PB8L23;
PB8L25 = CARRY(PB8L25_cout_0);

--PB8L26 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[8]~117COUT1_202 at LC_X38_Y11_N0
--operation mode is arithmetic

PB8L26_cout_1 = RB1_constant_update_reg[24] & (F1_ADDRLOCK[24] # !PB8L23) # !RB1_constant_update_reg[24] & F1_ADDRLOCK[24] & !PB8L23;
PB8L26 = CARRY(PB8L26_cout_1);


--PB8_sout_node[9] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[9] at LC_X38_Y11_N1
--operation mode is arithmetic

PB8_sout_node[9]_carry_eqn = (!PB8L23 & PB8L25) # (PB8L23 & PB8L26);
PB8_sout_node[9]_lut_out = F1_ADDRLOCK[25] $ RB1_constant_update_reg[25] $ PB8_sout_node[9]_carry_eqn;
PB8_sout_node[9] = DFFEAS(PB8_sout_node[9]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L28 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[9]~121 at LC_X38_Y11_N1
--operation mode is arithmetic

PB8L28_cout_0 = F1_ADDRLOCK[25] & !RB1_constant_update_reg[25] & !PB8L25 # !F1_ADDRLOCK[25] & (!PB8L25 # !RB1_constant_update_reg[25]);
PB8L28 = CARRY(PB8L28_cout_0);

--PB8L29 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[9]~121COUT1_204 at LC_X38_Y11_N1
--operation mode is arithmetic

PB8L29_cout_1 = F1_ADDRLOCK[25] & !RB1_constant_update_reg[25] & !PB8L26 # !F1_ADDRLOCK[25] & (!PB8L26 # !RB1_constant_update_reg[25]);
PB8L29 = CARRY(PB8L29_cout_1);


--PB8_sout_node[10] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[10] at LC_X38_Y11_N2
--operation mode is arithmetic

PB8_sout_node[10]_carry_eqn = (!PB8L23 & PB8L28) # (PB8L23 & PB8L29);
PB8_sout_node[10]_lut_out = RB1_constant_update_reg[26] $ F1_ADDRLOCK[26] $ !PB8_sout_node[10]_carry_eqn;
PB8_sout_node[10] = DFFEAS(PB8_sout_node[10]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L31 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[10]~125 at LC_X38_Y11_N2
--operation mode is arithmetic

PB8L31_cout_0 = RB1_constant_update_reg[26] & (F1_ADDRLOCK[26] # !PB8L28) # !RB1_constant_update_reg[26] & F1_ADDRLOCK[26] & !PB8L28;
PB8L31 = CARRY(PB8L31_cout_0);

--PB8L32 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[10]~125COUT1_206 at LC_X38_Y11_N2
--operation mode is arithmetic

PB8L32_cout_1 = RB1_constant_update_reg[26] & (F1_ADDRLOCK[26] # !PB8L29) # !RB1_constant_update_reg[26] & F1_ADDRLOCK[26] & !PB8L29;
PB8L32 = CARRY(PB8L32_cout_1);


--PB8_sout_node[11] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[11] at LC_X38_Y11_N3
--operation mode is arithmetic

PB8_sout_node[11]_carry_eqn = (!PB8L23 & PB8L31) # (PB8L23 & PB8L32);
PB8_sout_node[11]_lut_out = F1_ADDRLOCK[27] $ RB1_constant_update_reg[27] $ PB8_sout_node[11]_carry_eqn;
PB8_sout_node[11] = DFFEAS(PB8_sout_node[11]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L34 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[11]~129 at LC_X38_Y11_N3
--operation mode is arithmetic

PB8L34_cout_0 = F1_ADDRLOCK[27] & !RB1_constant_update_reg[27] & !PB8L31 # !F1_ADDRLOCK[27] & (!PB8L31 # !RB1_constant_update_reg[27]);
PB8L34 = CARRY(PB8L34_cout_0);

--PB8L35 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[11]~129COUT1_208 at LC_X38_Y11_N3
--operation mode is arithmetic

PB8L35_cout_1 = F1_ADDRLOCK[27] & !RB1_constant_update_reg[27] & !PB8L32 # !F1_ADDRLOCK[27] & (!PB8L32 # !RB1_constant_update_reg[27]);
PB8L35 = CARRY(PB8L35_cout_1);


--PB8_sout_node[12] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12] at LC_X38_Y11_N4
--operation mode is arithmetic

PB8_sout_node[12]_carry_eqn = (!PB8L23 & PB8L34) # (PB8L23 & PB8L35);
PB8_sout_node[12]_lut_out = RB1_constant_update_reg[28] $ F1_ADDRLOCK[28] $ !PB8_sout_node[12]_carry_eqn;
PB8_sout_node[12] = DFFEAS(PB8_sout_node[12]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L37 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12]~133 at LC_X38_Y11_N4
--operation mode is arithmetic

PB8L37 = CARRY(RB1_constant_update_reg[28] & (F1_ADDRLOCK[28] # !PB8L35) # !RB1_constant_update_reg[28] & F1_ADDRLOCK[28] & !PB8L35);


--PB8_sout_node[13] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[13] at LC_X38_Y11_N5
--operation mode is arithmetic

PB8_sout_node[13]_carry_eqn = PB8L37;
PB8_sout_node[13]_lut_out = RB1_constant_update_reg[29] $ F1_ADDRLOCK[29] $ PB8_sout_node[13]_carry_eqn;
PB8_sout_node[13] = DFFEAS(PB8_sout_node[13]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L39 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[13]~137 at LC_X38_Y11_N5
--operation mode is arithmetic

PB8L39_cout_0 = RB1_constant_update_reg[29] & !F1_ADDRLOCK[29] & !PB8L37 # !RB1_constant_update_reg[29] & (!PB8L37 # !F1_ADDRLOCK[29]);
PB8L39 = CARRY(PB8L39_cout_0);

--PB8L40 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[13]~137COUT1_210 at LC_X38_Y11_N5
--operation mode is arithmetic

PB8L40_cout_1 = RB1_constant_update_reg[29] & !F1_ADDRLOCK[29] & !PB8L37 # !RB1_constant_update_reg[29] & (!PB8L37 # !F1_ADDRLOCK[29]);
PB8L40 = CARRY(PB8L40_cout_1);


--PB8_sout_node[14] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[14] at LC_X38_Y11_N6
--operation mode is arithmetic

PB8_sout_node[14]_carry_eqn = (!PB8L37 & PB8L39) # (PB8L37 & PB8L40);
PB8_sout_node[14]_lut_out = F1_ADDRLOCK[30] $ RB1_constant_update_reg[30] $ !PB8_sout_node[14]_carry_eqn;
PB8_sout_node[14] = DFFEAS(PB8_sout_node[14]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L42 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[14]~141 at LC_X38_Y11_N6
--operation mode is arithmetic

PB8L42_cout_0 = F1_ADDRLOCK[30] & (RB1_constant_update_reg[30] # !PB8L39) # !F1_ADDRLOCK[30] & RB1_constant_update_reg[30] & !PB8L39;
PB8L42 = CARRY(PB8L42_cout_0);

--PB8L43 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[14]~141COUT1_212 at LC_X38_Y11_N6
--operation mode is arithmetic

PB8L43_cout_1 = F1_ADDRLOCK[30] & (RB1_constant_update_reg[30] # !PB8L40) # !F1_ADDRLOCK[30] & RB1_constant_update_reg[30] & !PB8L40;
PB8L43 = CARRY(PB8L43_cout_1);


--PB8_sout_node[15] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[15] at LC_X38_Y11_N7
--operation mode is normal

PB8_sout_node[15]_carry_eqn = (!PB8L37 & PB8L42) # (PB8L37 & PB8L43);
PB8_sout_node[15]_lut_out = F1_ADDROUT[8] $ (PB8_sout_node[15]_carry_eqn $ RB1_constant_update_reg[31]);
PB8_sout_node[15] = DFFEAS(PB8_sout_node[15]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );


--VB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X27_Y12_N7
--operation mode is normal

VB1_state[4] = AMPP_FUNCTION(A1L5, VB1_state[4], VB1_state[3], VB1_state[7], VCC, A1L7);


--VB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LC_X27_Y12_N4
--operation mode is normal

VB1_state[3] = AMPP_FUNCTION(A1L5, VB1_state[2], A1L7, VCC);


--H1_jtag_debug_mode_usr1 is sld_hub:sld_hub_inst|jtag_debug_mode_usr1 at LC_X27_Y13_N3
--operation mode is normal

H1_jtag_debug_mode_usr1 = AMPP_FUNCTION(A1L5, A1L30, Q5_dffs[1], A1L31, Q5_dffs[0], VB1_state[0], VB1_state[12]);


--RB1L72 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|name_gen~33 at LC_X28_Y14_N5
--operation mode is normal

RB1L72 = AMPP_FUNCTION(VB1_state[3], VB1_state[4], H1_jtag_debug_mode_usr1);


--TB8_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] at LC_X27_Y13_N6
--operation mode is normal

TB8_Q[0] = AMPP_FUNCTION(A1L5, TB3_Q[8], altera_internal_jtag, H1_CLRN_SIGNAL, H1L20);


--L1_WORD_SR[0] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|sld_rom_sr:\constant_logic_gen:name_gen:info_rom_sr|WORD_SR[0] at LC_X27_Y14_N9
--operation mode is normal

L1_WORD_SR[0] = AMPP_FUNCTION(A1L5, L1L16, L3_clear_signal, VB1_state[4], L1_WORD_SR[1], VCC, L1L14);


--TB5_Q[1] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] at LC_X27_Y11_N2
--operation mode is normal

TB5_Q[1] = AMPP_FUNCTION(A1L5, TB3_Q[1], TB7_Q[1], TB2_Q[0], H1_CLRN_SIGNAL, H1L21);


--TB5_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X27_Y11_N5
--operation mode is normal

TB5_Q[2] = AMPP_FUNCTION(A1L5, TB7_Q[2], TB3_Q[2], TB2_Q[0], H1_CLRN_SIGNAL, H1L21);


--RB1L75 is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|process2~42 at LC_X27_Y12_N1
--operation mode is normal

RB1L75 = AMPP_FUNCTION(TB5_Q[1], TB5_Q[2]);


--RB1_bypass_reg_out is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|bypass_reg_out at LC_X27_Y12_N5
--operation mode is normal

RB1_bypass_reg_out = AMPP_FUNCTION(A1L5, altera_internal_jtag, H1L30, RB1_bypass_reg_out, H1_CLRN_SIGNAL);


--TB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] at LC_X27_Y11_N9
--operation mode is normal

TB5_Q[0] = AMPP_FUNCTION(A1L5, TB3_Q[0], TB2_Q[0], TB7_Q[0], H1_CLRN_SIGNAL, H1L21);


--H1L9 is sld_hub:sld_hub_inst|hub_tdo~807 at LC_X27_Y12_N0
--operation mode is normal

H1L9 = AMPP_FUNCTION(L1_WORD_SR[0], RB1_bypass_reg_out, TB5_Q[0], RB1L75);


--RB1_constant_shift_reg[0] is lpm_constant0:inst2|lpm_constant0_lpm_constant_iia:lpm_constant0_lpm_constant_iia_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[0] at LC_X36_Y13_N7
--operation mode is normal

RB1_constant_shift_reg[0] = AMPP_FUNCTION(A1L5, RB1L76, RB1_constant_update_reg[0], RB1_constant_shift_reg[1], VB1_state[4], VCC, RB1L19);


--H1L10 is sld_hub:sld_hub_inst|hub_tdo~808 at LC_X27_Y12_N9
--operation mode is normal

H1L10 = AMPP_FUNCTION(TB5_Q[1], TB5_Q[2], TB5_Q[0], RB1_constant_shift_reg[0]);


--H1L11 is sld_hub:sld_hub_inst|hub_tdo~809 at LC_X27_Y12_N3
--operation mode is normal

H1L11 = AMPP_FUNCTION(TB8_Q[0], RB1L72, H1L10, H1L9);


--TB3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0] at LC_X29_Y13_N3
--operation mode is normal

TB3_Q[0] = AMPP_FUNCTION(A1L5, RB1_is_in_use_reg, M1L3, TB3_Q[1], H1L19, H1_CLRN_SIGNAL, VB1_state[4], TB3L4);


--VB1L18 is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state~13 at LC_X29_Y13_N6
--operation mode is normal

VB1L18 = AMPP_FUNCTION(VB1_state[3], VB1_state[4]);


--H1L12 is sld_hub:sld_hub_inst|hub_tdo~810 at LC_X29_Y14_N4
--operation mode is normal

H1L12 = AMPP_FUNCTION(VB1L18, H1_jtag_debug_mode_usr1, H1_hub_tdo, TB3_Q[0]);


--TB9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X28_Y14_N4
--operation mode is normal

TB9_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, TB3_Q[8], VCC, H1L20);


--L3_WORD_SR[0] is sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] at LC_X30_Y15_N7
--operation mode is normal

L3_WORD_SR[0] = AMPP_FUNCTION(A1L5, L3L26, L3L24, L3L25, L1L17, VCC, L3L20);


--H1_HUB_BYPASS_REG is sld_hub:sld_hub_inst|HUB_BYPASS_REG at LC_X28_Y13_N9
--operation mode is normal

H1_HUB_BYPASS_REG = AMPP_FUNCTION(A1L5, VB1_state[4], altera_internal_jtag, VCC);


--WB1_dffe1a[0] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[0] at LC_X28_Y13_N7
--operation mode is normal

WB1_dffe1a[0] = AMPP_FUNCTION(A1L5, TB3_Q[3], TB3_Q[1], TB3_Q[2], H1L28, H1_CLRN_SIGNAL, H1L3);


--H1L13 is sld_hub:sld_hub_inst|hub_tdo~811 at LC_X28_Y13_N8
--operation mode is normal