dds.fit.eqn

DDs直接数字频率合成器的源代码

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--JB1_q_a[9] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[9] at M4K_X33_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9] = JB1_q_a[9]_PORT_A_data_out_reg[0];

--JB1_q_a[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[0] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[0] = JB1_q_a[9]_PORT_A_data_out_reg[8];

--JB1_q_a[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[1] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[1] = JB1_q_a[9]_PORT_A_data_out_reg[7];

--JB1_q_a[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[2] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[2] = JB1_q_a[9]_PORT_A_data_out_reg[6];

--JB1_q_a[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[4] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[4] = JB1_q_a[9]_PORT_A_data_out_reg[5];

--JB1_q_a[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[5] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[5] = JB1_q_a[9]_PORT_A_data_out_reg[4];

--JB1_q_a[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[6] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[6] = JB1_q_a[9]_PORT_A_data_out_reg[3];

--JB1_q_a[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[7] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[7] = JB1_q_a[9]_PORT_A_data_out_reg[2];

--JB1_q_a[8] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[8] at M4K_X33_Y12
JB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[9]_PORT_A_address_reg = DFFE(JB1_q_a[9]_PORT_A_address, JB1_q_a[9]_clock_0, , , );
JB1_q_a[9]_clock_0 = GLOBAL(clk);
JB1_q_a[9]_PORT_A_data_out = MEMORY(, , JB1_q_a[9]_PORT_A_address_reg, , , , , , JB1_q_a[9]_clock_0, , , , , );
JB1_q_a[9]_PORT_A_data_out_reg = DFFE(JB1_q_a[9]_PORT_A_data_out, JB1_q_a[9]_clock_0, , , );
JB1_q_a[8] = JB1_q_a[9]_PORT_A_data_out_reg[1];


--JB1_q_a[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_pas:auto_generated|q_a[3] at M4K_X33_Y11
--RAM Block Operation Mode: ROM
--Port A Depth: 512, Port A Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10
--Port A Input: Registered, Port A Output: Registered
JB1_q_a[3]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
JB1_q_a[3]_PORT_A_address_reg = DFFE(JB1_q_a[3]_PORT_A_address, JB1_q_a[3]_clock_0, , , );
JB1_q_a[3]_clock_0 = GLOBAL(clk);
JB1_q_a[3]_PORT_A_data_out = MEMORY(, , JB1_q_a[3]_PORT_A_address_reg, , , , , , JB1_q_a[3]_clock_0, , , , , );
JB1_q_a[3]_PORT_A_data_out_reg = DFFE(JB1_q_a[3]_PORT_A_data_out, JB1_q_a[3]_clock_0, , , );
JB1_q_a[3] = JB1_q_a[3]_PORT_A_data_out_reg[0];


--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y13_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y13_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y13_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y13_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);


--F1_ADDRLOCK[23] is AddrLock:inst3|ADDRLOCK[23] at LC_X39_Y12_N9
--operation mode is arithmetic

F1_ADDRLOCK[23]_carry_eqn = (!F1L25 & F1L36) # (F1L25 & F1L37);
F1_ADDRLOCK[23]_lut_out = PB8_sout_node[7] $ F1_ADDRLOCK[23]_carry_eqn;
F1_ADDRLOCK[23] = DFFEAS(F1_ADDRLOCK[23]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L39 is AddrLock:inst3|ADDRLOCK[23]~139 at LC_X39_Y12_N9
--operation mode is arithmetic

F1L39 = CARRY(!F1L37 # !PB8_sout_node[7]);


--F1_ADDRLOCK[24] is AddrLock:inst3|ADDRLOCK[24] at LC_X39_Y11_N0
--operation mode is arithmetic

F1_ADDRLOCK[24]_carry_eqn = F1L39;
F1_ADDRLOCK[24]_lut_out = PB8_sout_node[8] $ !F1_ADDRLOCK[24]_carry_eqn;
F1_ADDRLOCK[24] = DFFEAS(F1_ADDRLOCK[24]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L41 is AddrLock:inst3|ADDRLOCK[24]~143 at LC_X39_Y11_N0
--operation mode is arithmetic

F1L41_cout_0 = PB8_sout_node[8] & !F1L39;
F1L41 = CARRY(F1L41_cout_0);

--F1L42 is AddrLock:inst3|ADDRLOCK[24]~143COUT1_240 at LC_X39_Y11_N0
--operation mode is arithmetic

F1L42_cout_1 = PB8_sout_node[8] & !F1L39;
F1L42 = CARRY(F1L42_cout_1);


--F1_ADDRLOCK[25] is AddrLock:inst3|ADDRLOCK[25] at LC_X39_Y11_N1
--operation mode is arithmetic

F1_ADDRLOCK[25]_carry_eqn = (!F1L39 & F1L41) # (F1L39 & F1L42);
F1_ADDRLOCK[25]_lut_out = PB8_sout_node[9] $ (F1_ADDRLOCK[25]_carry_eqn);
F1_ADDRLOCK[25] = DFFEAS(F1_ADDRLOCK[25]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L44 is AddrLock:inst3|ADDRLOCK[25]~147 at LC_X39_Y11_N1
--operation mode is arithmetic

F1L44_cout_0 = !F1L41 # !PB8_sout_node[9];
F1L44 = CARRY(F1L44_cout_0);

--F1L45 is AddrLock:inst3|ADDRLOCK[25]~147COUT1_242 at LC_X39_Y11_N1
--operation mode is arithmetic

F1L45_cout_1 = !F1L42 # !PB8_sout_node[9];
F1L45 = CARRY(F1L45_cout_1);


--F1_ADDRLOCK[26] is AddrLock:inst3|ADDRLOCK[26] at LC_X39_Y11_N2
--operation mode is arithmetic

F1_ADDRLOCK[26]_carry_eqn = (!F1L39 & F1L44) # (F1L39 & F1L45);
F1_ADDRLOCK[26]_lut_out = PB8_sout_node[10] $ !F1_ADDRLOCK[26]_carry_eqn;
F1_ADDRLOCK[26] = DFFEAS(F1_ADDRLOCK[26]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L47 is AddrLock:inst3|ADDRLOCK[26]~151 at LC_X39_Y11_N2
--operation mode is arithmetic

F1L47_cout_0 = PB8_sout_node[10] & !F1L44;
F1L47 = CARRY(F1L47_cout_0);

--F1L48 is AddrLock:inst3|ADDRLOCK[26]~151COUT1_244 at LC_X39_Y11_N2
--operation mode is arithmetic

F1L48_cout_1 = PB8_sout_node[10] & !F1L45;
F1L48 = CARRY(F1L48_cout_1);


--F1_ADDRLOCK[27] is AddrLock:inst3|ADDRLOCK[27] at LC_X39_Y11_N3
--operation mode is arithmetic

F1_ADDRLOCK[27]_carry_eqn = (!F1L39 & F1L47) # (F1L39 & F1L48);
F1_ADDRLOCK[27]_lut_out = PB8_sout_node[11] $ (F1_ADDRLOCK[27]_carry_eqn);
F1_ADDRLOCK[27] = DFFEAS(F1_ADDRLOCK[27]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L50 is AddrLock:inst3|ADDRLOCK[27]~155 at LC_X39_Y11_N3
--operation mode is arithmetic

F1L50_cout_0 = !F1L47 # !PB8_sout_node[11];
F1L50 = CARRY(F1L50_cout_0);

--F1L51 is AddrLock:inst3|ADDRLOCK[27]~155COUT1_246 at LC_X39_Y11_N3
--operation mode is arithmetic

F1L51_cout_1 = !F1L48 # !PB8_sout_node[11];
F1L51 = CARRY(F1L51_cout_1);


--F1_ADDRLOCK[28] is AddrLock:inst3|ADDRLOCK[28] at LC_X39_Y11_N4
--operation mode is arithmetic

F1_ADDRLOCK[28]_carry_eqn = (!F1L39 & F1L50) # (F1L39 & F1L51);
F1_ADDRLOCK[28]_lut_out = PB8_sout_node[12] $ !F1_ADDRLOCK[28]_carry_eqn;
F1_ADDRLOCK[28] = DFFEAS(F1_ADDRLOCK[28]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L53 is AddrLock:inst3|ADDRLOCK[28]~159 at LC_X39_Y11_N4
--operation mode is arithmetic

F1L53 = CARRY(PB8_sout_node[12] & !F1L51);


--F1_ADDRLOCK[29] is AddrLock:inst3|ADDRLOCK[29] at LC_X39_Y11_N5
--operation mode is arithmetic

F1_ADDRLOCK[29]_carry_eqn = F1L53;
F1_ADDRLOCK[29]_lut_out = PB8_sout_node[13] $ F1_ADDRLOCK[29]_carry_eqn;
F1_ADDRLOCK[29] = DFFEAS(F1_ADDRLOCK[29]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L55 is AddrLock:inst3|ADDRLOCK[29]~163 at LC_X39_Y11_N5
--operation mode is arithmetic

F1L55_cout_0 = !F1L53 # !PB8_sout_node[13];
F1L55 = CARRY(F1L55_cout_0);

--F1L56 is AddrLock:inst3|ADDRLOCK[29]~163COUT1_248 at LC_X39_Y11_N5
--operation mode is arithmetic

F1L56_cout_1 = !F1L53 # !PB8_sout_node[13];
F1L56 = CARRY(F1L56_cout_1);


--F1_ADDRLOCK[30] is AddrLock:inst3|ADDRLOCK[30] at LC_X39_Y11_N6
--operation mode is arithmetic

F1_ADDRLOCK[30]_carry_eqn = (!F1L53 & F1L55) # (F1L53 & F1L56);
F1_ADDRLOCK[30]_lut_out = PB8_sout_node[14] $ (!F1_ADDRLOCK[30]_carry_eqn);
F1_ADDRLOCK[30] = DFFEAS(F1_ADDRLOCK[30]_lut_out, GLOBAL(clk), VCC, , , , , , );

--F1L58 is AddrLock:inst3|ADDRLOCK[30]~167 at LC_X39_Y11_N6
--operation mode is arithmetic

F1L58_cout_0 = PB8_sout_node[14] & (!F1L55);
F1L58 = CARRY(F1L58_cout_0);

--F1L59 is AddrLock:inst3|ADDRLOCK[30]~167COUT1_250 at LC_X39_Y11_N6
--operation mode is arithmetic

F1L59_cout_1 = PB8_sout_node[14] & (!F1L56);
F1L59 = CARRY(F1L59_cout_1);


--F1_ADDROUT[8] is AddrLock:inst3|ADDROUT[8] at LC_X39_Y11_N7
--operation mode is normal

F1_ADDROUT[8]_carry_eqn = (!F1L53 & F1L58) # (F1L53 & F1L59);
F1_ADDROUT[8]_lut_out = F1_ADDROUT[8]_carry_eqn $ PB8_sout_node[15];
F1_ADDROUT[8] = DFFEAS(F1_ADDROUT[8]_lut_out, GLOBAL(clk), VCC, , , , , , );


--H1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LC_X29_Y14_N2
--operation mode is normal

H1_hub_tdo = AMPP_FUNCTION(!A1L5, H1L11, H1L18, H1L14, H1L17, !VB1_state[8]);


--PB8_sout_node[7] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7] at LC_X38_Y12_N9
--operation mode is arithmetic

PB8_sout_node[7]_carry_eqn = (!PB8L9 & PB8L20) # (PB8L9 & PB8L21);
PB8_sout_node[7]_lut_out = RB1_constant_update_reg[23] $ F1_ADDRLOCK[23] $ !PB8_sout_node[7]_carry_eqn;
PB8_sout_node[7] = DFFEAS(PB8_sout_node[7]_lut_out, GLOBAL(SB1__clk0), VCC, , , , , , );

--PB8L23 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]~113 at LC_X38_Y12_N9
--operation mode is arithmetic

PB8L23 = CARRY(RB1_constant_update_reg[23] & (!PB8L21 # !F1_ADDRLOCK[23]) # !RB1_constant_update_reg[23] & !F1_ADDRLOCK[23] & !PB8L21);


--F1_ADDRLOCK[22] is AddrLock:inst3|ADDRLOCK[22] at LC_X39_Y12_N8
--operation mode is arithmetic