dds.tan.summary

来自「DDs直接数字频率合成器的源代码」· SUMMARY 代码 · 共 107 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 0.433 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_ogi:auto_generated|dffe1a[7]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.600 ns
From           : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_9d31:auto_generated|q_a[7]
To             : q_out[7]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.117 ns
From           : altera_internal_jtag
To             : lpm_constant0:inst2|lpm_constant0_lpm_constant_ama:lpm_constant0_lpm_constant_ama_component|sld_mod_ram_rom:mgl_prim1|constant_shift_reg[31]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : -0.960 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]
To             : AddrLock:inst3|ADDROUT[8]
From Clock     : DPLL:inst4|altpll:altpll_component|_clk0
To Clock       : clk
Failed Paths   : 130

Type           : Clock Setup: 'DPLL:inst4|altpll:altpll_component|_clk0'
Slack          : 6.704 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : AddrLock:inst3|ADDRLOCK[16]
To             : lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[15]
From Clock     : clk
To Clock       : DPLL:inst4|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 59.22 MHz ( period = 16.886 ns )
From           : sld_hub:sld_hub_inst|jtag_debug_mode_usr1
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : 0.822 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'DPLL:inst4|altpll:altpll_component|_clk0'
Slack          : 3.613 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : AddrLock:inst3|ADDRLOCK[5]
To             : lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[5]
From Clock     : clk
To Clock       : DPLL:inst4|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 130

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