dds51.map.eqn

DDs直接数字频率合成器的源代码

--XB1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1]
--operation mode is normal

XB1_dffe1a[1] = AMPP_FUNCTION(A1L5, H1L41, UB3_Q[1], UB3_Q[2], UB3_Q[3], H1_CLRN_SIGNAL, H1L5);


--WB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8]
--operation mode is normal

WB1_state[8] = AMPP_FUNCTION(A1L5, WB1_state[5], WB1_state[7], VCC, !A1L7);


--H1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28
--operation mode is normal

H1L1 = AMPP_FUNCTION(WB1_state[8], H1_OK_TO_UPDATE_IR_Q, XB1_dffe1a[2], XB1_dffe1a[1]);


--Q5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1]
--operation mode is normal

Q5_dffs[1] = AMPP_FUNCTION(A1L5, Q5_dffs[2], WB1_state[0], WB1_state[11]);


--Q5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
--operation mode is normal

Q5_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, WB1_state[0], WB1_state[11]);


--Q5_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8]
--operation mode is normal

Q5_dffs[8] = AMPP_FUNCTION(A1L5, Q5_dffs[9], WB1_state[0], WB1_state[11]);


--Q5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7]
--operation mode is normal

Q5_dffs[7] = AMPP_FUNCTION(A1L5, Q5_dffs[8], WB1_state[0], WB1_state[11]);


--Q5_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6]
--operation mode is normal

Q5_dffs[6] = AMPP_FUNCTION(A1L5, Q5_dffs[7], WB1_state[0], WB1_state[11]);


--A1L26 is rtl~101
--operation mode is normal

A1L26 = !Q5_dffs[9] & !Q5_dffs[8] & !Q5_dffs[7] & !Q5_dffs[6];


--Q5_dffs[3] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[3]
--operation mode is normal

Q5_dffs[3] = AMPP_FUNCTION(A1L5, Q5_dffs[4], WB1_state[0], WB1_state[11]);


--Q5_dffs[2] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[2]
--operation mode is normal

Q5_dffs[2] = AMPP_FUNCTION(A1L5, Q5_dffs[3], WB1_state[0], WB1_state[11]);


--Q5_dffs[5] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[5]
--operation mode is normal

Q5_dffs[5] = AMPP_FUNCTION(A1L5, Q5_dffs[6], WB1_state[0], WB1_state[11]);


--Q5_dffs[4] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[4]
--operation mode is normal

Q5_dffs[4] = AMPP_FUNCTION(A1L5, Q5_dffs[5], WB1_state[0], WB1_state[11]);


--A1L27 is rtl~102
--operation mode is normal

A1L27 = Q5_dffs[3] & Q5_dffs[2] & !Q5_dffs[5] & !Q5_dffs[4];


--Q5_dffs[0] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[0]
--operation mode is normal

Q5_dffs[0] = AMPP_FUNCTION(A1L5, Q5_dffs[1], WB1_state[0], WB1_state[11]);


--RB8_sout_node[7] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]
--operation mode is arithmetic

RB8_sout_node[7]_carry_eqn = RB8L15;
RB8_sout_node[7]_lut_out = LB2_constant_update_reg[23] $ F1_ADDRLOCK[23] $ RB8_sout_node[7]_carry_eqn;
RB8_sout_node[7] = DFFEAS(RB8_sout_node[7]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L17 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[7]~113
--operation mode is arithmetic

RB8L17 = CARRY(LB2_constant_update_reg[23] & !F1_ADDRLOCK[23] & !RB8L15 # !LB2_constant_update_reg[23] & (!RB8L15 # !F1_ADDRLOCK[23]));


--F1_ADDRLOCK[22] is AddrLock:inst3|ADDRLOCK[22]
--operation mode is arithmetic

F1_ADDRLOCK[22]_carry_eqn = F1L29;
F1_ADDRLOCK[22]_lut_out = RB8_sout_node[6] $ (!F1_ADDRLOCK[22]_carry_eqn);
F1_ADDRLOCK[22] = DFFEAS(F1_ADDRLOCK[22]_lut_out, clk, VCC, , , , , , );

--F1L31 is AddrLock:inst3|ADDRLOCK[22]~171
--operation mode is arithmetic

F1L31 = CARRY(RB8_sout_node[6] & (!F1L29));


--RB8_sout_node[8] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[8]
--operation mode is arithmetic

RB8_sout_node[8]_carry_eqn = RB8L17;
RB8_sout_node[8]_lut_out = LB2_constant_update_reg[24] $ F1_ADDRLOCK[24] $ !RB8_sout_node[8]_carry_eqn;
RB8_sout_node[8] = DFFEAS(RB8_sout_node[8]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L19 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[8]~117
--operation mode is arithmetic

RB8L19 = CARRY(LB2_constant_update_reg[24] & (F1_ADDRLOCK[24] # !RB8L17) # !LB2_constant_update_reg[24] & F1_ADDRLOCK[24] & !RB8L17);


--RB8_sout_node[9] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[9]
--operation mode is arithmetic

RB8_sout_node[9]_carry_eqn = RB8L19;
RB8_sout_node[9]_lut_out = LB2_constant_update_reg[25] $ F1_ADDRLOCK[25] $ RB8_sout_node[9]_carry_eqn;
RB8_sout_node[9] = DFFEAS(RB8_sout_node[9]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L21 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[9]~121
--operation mode is arithmetic

RB8L21 = CARRY(LB2_constant_update_reg[25] & !F1_ADDRLOCK[25] & !RB8L19 # !LB2_constant_update_reg[25] & (!RB8L19 # !F1_ADDRLOCK[25]));


--RB8_sout_node[10] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[10]
--operation mode is arithmetic

RB8_sout_node[10]_carry_eqn = RB8L21;
RB8_sout_node[10]_lut_out = LB2_constant_update_reg[26] $ F1_ADDRLOCK[26] $ !RB8_sout_node[10]_carry_eqn;
RB8_sout_node[10] = DFFEAS(RB8_sout_node[10]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L23 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[10]~125
--operation mode is arithmetic

RB8L23 = CARRY(LB2_constant_update_reg[26] & (F1_ADDRLOCK[26] # !RB8L21) # !LB2_constant_update_reg[26] & F1_ADDRLOCK[26] & !RB8L21);


--RB8_sout_node[11] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[11]
--operation mode is arithmetic

RB8_sout_node[11]_carry_eqn = RB8L23;
RB8_sout_node[11]_lut_out = LB2_constant_update_reg[27] $ F1_ADDRLOCK[27] $ RB8_sout_node[11]_carry_eqn;
RB8_sout_node[11] = DFFEAS(RB8_sout_node[11]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L25 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[11]~129
--operation mode is arithmetic

RB8L25 = CARRY(LB2_constant_update_reg[27] & !F1_ADDRLOCK[27] & !RB8L23 # !LB2_constant_update_reg[27] & (!RB8L23 # !F1_ADDRLOCK[27]));


--RB8_sout_node[12] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12]
--operation mode is arithmetic

RB8_sout_node[12]_carry_eqn = RB8L25;
RB8_sout_node[12]_lut_out = LB2_constant_update_reg[28] $ F1_ADDRLOCK[28] $ !RB8_sout_node[12]_carry_eqn;
RB8_sout_node[12] = DFFEAS(RB8_sout_node[12]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L27 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[12]~133
--operation mode is arithmetic

RB8L27 = CARRY(LB2_constant_update_reg[28] & (F1_ADDRLOCK[28] # !RB8L25) # !LB2_constant_update_reg[28] & F1_ADDRLOCK[28] & !RB8L25);


--RB8_sout_node[13] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[13]
--operation mode is arithmetic

RB8_sout_node[13]_carry_eqn = RB8L27;
RB8_sout_node[13]_lut_out = LB2_constant_update_reg[29] $ F1_ADDRLOCK[29] $ RB8_sout_node[13]_carry_eqn;
RB8_sout_node[13] = DFFEAS(RB8_sout_node[13]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L29 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[13]~137
--operation mode is arithmetic

RB8L29 = CARRY(LB2_constant_update_reg[29] & !F1_ADDRLOCK[29] & !RB8L27 # !LB2_constant_update_reg[29] & (!RB8L27 # !F1_ADDRLOCK[29]));


--RB8_sout_node[14] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[14]
--operation mode is arithmetic

RB8_sout_node[14]_carry_eqn = RB8L29;
RB8_sout_node[14]_lut_out = LB2_constant_update_reg[30] $ F1_ADDRLOCK[30] $ !RB8_sout_node[14]_carry_eqn;
RB8_sout_node[14] = DFFEAS(RB8_sout_node[14]_lut_out, TB1__clk0, VCC, , , , , , );

--RB8L31 is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[14]~141
--operation mode is arithmetic

RB8L31 = CARRY(LB2_constant_update_reg[30] & (F1_ADDRLOCK[30] # !RB8L29) # !LB2_constant_update_reg[30] & F1_ADDRLOCK[30] & !RB8L29);


--RB8_sout_node[15] is lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[15]
--operation mode is normal

RB8_sout_node[15]_carry_eqn = RB8L31;
RB8_sout_node[15]_lut_out = LB2_constant_update_reg[31] $ F1_ADDROUT[8] $ RB8_sout_node[15]_carry_eqn;
RB8_sout_node[15] = DFFEAS(RB8_sout_node[15]_lut_out, TB1__clk0, VCC, , , , , , );


--UB6_Q[3] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3]
--operation mode is normal

UB6_Q[3] = AMPP_FUNCTION(A