dds51.map.eqn

DDs直接数字频率合成器的源代码

LB1L25 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[4], LB1L23);


--LB1_ram_rom_addr_reg[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[5] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], !UB6_Q[0], LB1L10, LB1L25);

--LB1L27 is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5]~156
--operation mode is arithmetic

LB1L27 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[5], LB1L25);


--LB1_ram_rom_addr_reg[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[6] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], !UB6_Q[0], LB1L10, LB1L27);

--LB1L29 is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[6]~160
--operation mode is arithmetic

LB1L29 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[6], LB1L27);


--LB1_ram_rom_addr_reg[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]
--operation mode is arithmetic

LB1_ram_rom_addr_reg[7] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8], !UB6_Q[0], LB1L10, LB1L29);

--LB1L31 is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[7]~164
--operation mode is arithmetic

LB1L31 = AMPP_FUNCTION(LB1_ram_rom_addr_reg[7], LB1L29);


--LB1_ram_rom_addr_reg[8] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[8]
--operation mode is normal

LB1_ram_rom_addr_reg[8] = AMPP_FUNCTION(A1L5, LB1_ram_rom_addr_reg[8], altera_internal_jtag, !UB6_Q[0], LB1L10, LB1L31);


--LB1_ram_rom_data_reg[8] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[8]
--operation mode is normal

LB1_ram_rom_data_reg[8] = AMPP_FUNCTION(A1L5, KB1_q_b[8], LB1_ram_rom_data_reg[9], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

LB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, KB1_q_b[7], LB1_ram_rom_data_reg[8], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
--operation mode is normal

LB1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L5, KB1_q_b[6], LB1_ram_rom_data_reg[7], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
--operation mode is normal

LB1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L5, KB1_q_b[5], LB1_ram_rom_data_reg[6], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
--operation mode is normal

LB1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L5, KB1_q_b[4], LB1_ram_rom_data_reg[5], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

LB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, KB1_q_b[3], LB1_ram_rom_data_reg[4], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
--operation mode is normal

LB1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, KB1_q_b[2], LB1_ram_rom_data_reg[3], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
--operation mode is normal

LB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, KB1_q_b[1], LB1_ram_rom_data_reg[2], LB1L11, VCC, LB1L44);


--LB1_ram_rom_data_reg[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

LB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, KB1_q_b[0], LB1_ram_rom_data_reg[1], LB1L11, VCC, LB1L44);


--H1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo
--operation mode is normal

H1_hub_tdo = AMPP_FUNCTION(!A1L5, H1L15, H1L18, H1L21, H1L24, !WB1_state[8]);


--WB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4]
--operation mode is normal

WB1_state[4] = AMPP_FUNCTION(A1L5, WB1_state[7], WB1_state[3], WB1_state[4], VCC, A1L7);


--WB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3]
--operation mode is normal

WB1_state[3] = AMPP_FUNCTION(A1L5, WB1_state[2], A1L7, VCC);


--UB9_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
--operation mode is normal

UB9_Q[2] = AMPP_FUNCTION(A1L5, UB3_Q[2], H1_CLRN_SIGNAL, H1L8);


--UB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal

UB3_Q[2] = AMPP_FUNCTION(A1L5, UB3_Q[3], UB3L3, H1L34, M1L4, H1_CLRN_SIGNAL, UB3L4);


--H1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL
--operation mode is normal

H1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, WB1_state[1], UB1_Q[0], VCC);


--H1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
--operation mode is normal

H1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, H1_jtag_debug_mode_usr1, H1_OK_TO_UPDATE_IR_Q, WB1_state[4], WB1_state[8], VCC);


--H1L9 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~27
--operation mode is normal

H1L9 = AMPP_FUNCTION(WB1_state[5], H1_OK_TO_UPDATE_IR_Q);


--UB11_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
--operation mode is normal

UB11_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, UB3_Q[8], VCC, H1L27);


--XB1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2]
--operation mode is normal

XB1_dffe1a[2] = AMPP_FUNCTION(A1L5, UB3_Q[2], H1L41, UB3_Q[3], UB3_Q[1], H1_CLRN_SIGNAL, H1L5);


--H1L28 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~179
--operation mode is normal

H1L28 = AMPP_FUNCTION(UB11_Q[0], XB1_dffe1a[2]);


--H1L29 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~180
--operation mode is normal

H1L29 = AMPP_FUNCTION(H1L9, H1L28, UB10_Q[0], UB2_Q[0]);


--UB3_Q[8] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8]
--operation mode is normal

UB3_Q[8] = AMPP_FUNCTION(A1L5, altera_internal_jtag, H1_CLRN_SIGNAL, WB1_state[4], H1L37);


--H1L27 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21
--operation mode is normal

H1L27 = AMPP_FUNCTION(A1L7, WB1_state[4], H1_jtag_debug_mode_usr1, H1_OK_TO_UPDATE_IR_Q);


--H1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0
--operation mode is normal

H1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, A1L26, A1L27, Q5_dffs[1], Q5_dffs[0], WB1_state[0], WB1_state[12]);


--H1L41 is sld_hub:sld_hub_inst|jtag_debug_mode~2
--operation mode is normal

H1L41 = AMPP_FUNCTION(H1_jtag_debug_mode_usr1, H1_jtag_debug_mode_usr0);


--WB1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12]
--operation mode is normal

WB1_state[12] = AMPP_FUNCTION(A1L5, WB1_state[11], WB1_state[10], VCC, !A1L7);


--WB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2]
--operation mode is normal

WB1_state[2] = AMPP_FUNCTION(A1L5, WB1_state[8], WB1_state[1], WB1_state[15], VCC, !A1L7);


--H1L42 is sld_hub:sld_hub_inst|jtag_debug_mode~171
--operation mode is normal

H1L42 = AMPP_FUNCTION(WB1_state[12], A1L7, WB1_state[2]);


--WB1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15]
--operation mode is normal

WB1_state[15] = AMPP_FUNCTION(A1L5, WB1_state[12], WB1_state[14], VCC, !A1L7);


--WB1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0]
--operation mode is normal

WB1_state[0] = AMPP_FUNCTION(A1L5, A1L7, WB1_state[9], WB1L19, WB1_state[0], VCC);