dds51.map.eqn

DDs直接数字频率合成器的源代码

--KB1_q_a[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[4]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10, Port B Logical Depth: 512, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[4]_PORT_A_data_in = VCC;
KB1_q_a[4]_PORT_A_data_in_reg = DFFE(KB1_q_a[4]_PORT_A_data_in, KB1_q_a[4]_clock_0, , , );
KB1_q_a[4]_PORT_B_data_in = LB1_ram_rom_data_reg[4];
KB1_q_a[4]_PORT_B_data_in_reg = DFFE(KB1_q_a[4]_PORT_B_data_in, KB1_q_a[4]_clock_1, , , );
KB1_q_a[4]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[4]_PORT_A_address_reg = DFFE(KB1_q_a[4]_PORT_A_address, KB1_q_a[4]_clock_0, , , );
KB1_q_a[4]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[4]_PORT_B_address_reg = DFFE(KB1_q_a[4]_PORT_B_address, KB1_q_a[4]_clock_1, , , );
KB1_q_a[4]_PORT_A_write_enable = GND;
KB1_q_a[4]_PORT_A_write_enable_reg = DFFE(KB1_q_a[4]_PORT_A_write_enable, KB1_q_a[4]_clock_0, , , );
KB1_q_a[4]_PORT_B_write_enable = LB1L2;
KB1_q_a[4]_PORT_B_write_enable_reg = DFFE(KB1_q_a[4]_PORT_B_write_enable, KB1_q_a[4]_clock_1, , , );
KB1_q_a[4]_clock_0 = clk;
KB1_q_a[4]_clock_1 = A1L5;
KB1_q_a[4]_PORT_A_data_out = MEMORY(KB1_q_a[4]_PORT_A_data_in_reg, KB1_q_a[4]_PORT_B_data_in_reg, KB1_q_a[4]_PORT_A_address_reg, KB1_q_a[4]_PORT_B_address_reg, KB1_q_a[4]_PORT_A_write_enable_reg, KB1_q_a[4]_PORT_B_write_enable_reg, , , KB1_q_a[4]_clock_0, KB1_q_a[4]_clock_1, , , , );
KB1_q_a[4]_PORT_A_data_out_reg = DFFE(KB1_q_a[4]_PORT_A_data_out, KB1_q_a[4]_clock_0, , , );
KB1_q_a[4] = KB1_q_a[4]_PORT_A_data_out_reg[0];

--KB1_q_b[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_b[4]
KB1_q_b[4]_PORT_A_data_in = VCC;
KB1_q_b[4]_PORT_A_data_in_reg = DFFE(KB1_q_b[4]_PORT_A_data_in, KB1_q_b[4]_clock_0, , , );
KB1_q_b[4]_PORT_B_data_in = LB1_ram_rom_data_reg[4];
KB1_q_b[4]_PORT_B_data_in_reg = DFFE(KB1_q_b[4]_PORT_B_data_in, KB1_q_b[4]_clock_1, , , );
KB1_q_b[4]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_b[4]_PORT_A_address_reg = DFFE(KB1_q_b[4]_PORT_A_address, KB1_q_b[4]_clock_0, , , );
KB1_q_b[4]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_b[4]_PORT_B_address_reg = DFFE(KB1_q_b[4]_PORT_B_address, KB1_q_b[4]_clock_1, , , );
KB1_q_b[4]_PORT_A_write_enable = GND;
KB1_q_b[4]_PORT_A_write_enable_reg = DFFE(KB1_q_b[4]_PORT_A_write_enable, KB1_q_b[4]_clock_0, , , );
KB1_q_b[4]_PORT_B_write_enable = LB1L2;
KB1_q_b[4]_PORT_B_write_enable_reg = DFFE(KB1_q_b[4]_PORT_B_write_enable, KB1_q_b[4]_clock_1, , , );
KB1_q_b[4]_clock_0 = clk;
KB1_q_b[4]_clock_1 = A1L5;
KB1_q_b[4]_PORT_B_data_out = MEMORY(KB1_q_b[4]_PORT_A_data_in_reg, KB1_q_b[4]_PORT_B_data_in_reg, KB1_q_b[4]_PORT_A_address_reg, KB1_q_b[4]_PORT_B_address_reg, KB1_q_b[4]_PORT_A_write_enable_reg, KB1_q_b[4]_PORT_B_write_enable_reg, , , KB1_q_b[4]_clock_0, KB1_q_b[4]_clock_1, , , , );
KB1_q_b[4] = KB1_q_b[4]_PORT_B_data_out[0];


--KB1_q_a[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10, Port B Logical Depth: 512, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[3]_PORT_A_data_in = VCC;
KB1_q_a[3]_PORT_A_data_in_reg = DFFE(KB1_q_a[3]_PORT_A_data_in, KB1_q_a[3]_clock_0, , , );
KB1_q_a[3]_PORT_B_data_in = LB1_ram_rom_data_reg[3];
KB1_q_a[3]_PORT_B_data_in_reg = DFFE(KB1_q_a[3]_PORT_B_data_in, KB1_q_a[3]_clock_1, , , );
KB1_q_a[3]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[3]_PORT_A_address_reg = DFFE(KB1_q_a[3]_PORT_A_address, KB1_q_a[3]_clock_0, , , );
KB1_q_a[3]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[3]_PORT_B_address_reg = DFFE(KB1_q_a[3]_PORT_B_address, KB1_q_a[3]_clock_1, , , );
KB1_q_a[3]_PORT_A_write_enable = GND;
KB1_q_a[3]_PORT_A_write_enable_reg = DFFE(KB1_q_a[3]_PORT_A_write_enable, KB1_q_a[3]_clock_0, , , );
KB1_q_a[3]_PORT_B_write_enable = LB1L2;
KB1_q_a[3]_PORT_B_write_enable_reg = DFFE(KB1_q_a[3]_PORT_B_write_enable, KB1_q_a[3]_clock_1, , , );
KB1_q_a[3]_clock_0 = clk;
KB1_q_a[3]_clock_1 = A1L5;
KB1_q_a[3]_PORT_A_data_out = MEMORY(KB1_q_a[3]_PORT_A_data_in_reg, KB1_q_a[3]_PORT_B_data_in_reg, KB1_q_a[3]_PORT_A_address_reg, KB1_q_a[3]_PORT_B_address_reg, KB1_q_a[3]_PORT_A_write_enable_reg, KB1_q_a[3]_PORT_B_write_enable_reg, , , KB1_q_a[3]_clock_0, KB1_q_a[3]_clock_1, , , , );
KB1_q_a[3]_PORT_A_data_out_reg = DFFE(KB1_q_a[3]_PORT_A_data_out, KB1_q_a[3]_clock_0, , , );
KB1_q_a[3] = KB1_q_a[3]_PORT_A_data_out_reg[0];

--KB1_q_b[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_b[3]
KB1_q_b[3]_PORT_A_data_in = VCC;
KB1_q_b[3]_PORT_A_data_in_reg = DFFE(KB1_q_b[3]_PORT_A_data_in, KB1_q_b[3]_clock_0, , , );
KB1_q_b[3]_PORT_B_data_in = LB1_ram_rom_data_reg[3];
KB1_q_b[3]_PORT_B_data_in_reg = DFFE(KB1_q_b[3]_PORT_B_data_in, KB1_q_b[3]_clock_1, , , );
KB1_q_b[3]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_b[3]_PORT_A_address_reg = DFFE(KB1_q_b[3]_PORT_A_address, KB1_q_b[3]_clock_0, , , );
KB1_q_b[3]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_b[3]_PORT_B_address_reg = DFFE(KB1_q_b[3]_PORT_B_address, KB1_q_b[3]_clock_1, , , );
KB1_q_b[3]_PORT_A_write_enable = GND;
KB1_q_b[3]_PORT_A_write_enable_reg = DFFE(KB1_q_b[3]_PORT_A_write_enable, KB1_q_b[3]_clock_0, , , );
KB1_q_b[3]_PORT_B_write_enable = LB1L2;
KB1_q_b[3]_PORT_B_write_enable_reg = DFFE(KB1_q_b[3]_PORT_B_write_enable, KB1_q_b[3]_clock_1, , , );
KB1_q_b[3]_clock_0 = clk;
KB1_q_b[3]_clock_1 = A1L5;
KB1_q_b[3]_PORT_B_data_out = MEMORY(KB1_q_b[3]_PORT_A_data_in_reg, KB1_q_b[3]_PORT_B_data_in_reg, KB1_q_b[3]_PORT_A_address_reg, KB1_q_b[3]_PORT_B_address_reg, KB1_q_b[3]_PORT_A_write_enable_reg, KB1_q_b[3]_PORT_B_write_enable_reg, , , KB1_q_b[3]_clock_0, KB1_q_b[3]_clock_1, , , , );
KB1_q_b[3] = KB1_q_b[3]_PORT_B_data_out[0];


--KB1_q_a[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10, Port B Logical Depth: 512, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[2]_PORT_A_data_in = VCC;
KB1_q_a[2]_PORT_A_data_in_reg = DFFE(KB1_q_a[2]_PORT_A_data_in, KB1_q_a[2]_clock_0, , , );
KB1_q_a[2]_PORT_B_data_in = LB1_ram_rom_data_reg[2];
KB1_q_a[2]_PORT_B_data_in_reg = DFFE(KB1_q_a[2]_PORT_B_data_in, KB1_q_a[2]_clock_1, , , );
KB1_q_a[2]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[2]_PORT_A_address_reg = DFFE(KB1_q_a[2]_PORT_A_address, KB1_q_a[2]_clock_0, , , );
KB1_q_a[2]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[2]_PORT_B_address_reg = DFFE(KB1_q_a[2]_PORT_B_address, KB1_q_a[2]_clock_1, , , );
KB1_q_a[2]_PORT_A_write_enable = GND;
KB1_q_a[2]_PORT_A_write_enable_reg = DFFE(KB1_q_a[2]_PORT_A_write_enable, KB1_q_a[2]_clock_0, , , );
KB1_q_a[2]_PORT_B_write_enable = LB1L2;
KB1_q_a[2]_PORT_B_write_enable_reg = DFFE(KB1_q_a[2]_PORT_B_write_enable, KB1_q_a[2]_clock_1, , , );
KB1_q_a[2]_clock_0 = clk;
KB1_q_a[2]_clock_1 = A1L5;
KB1_q_a[2]_PORT_A_data_out = MEMORY(KB1_q_a[2]_PORT_A_data_in_reg, KB1_q_a[2]_PORT_B_data_in_reg, KB1_q_a[2]_PORT_A_address_reg, KB1_q_a[2]_PORT_B_address_reg, KB1_q_a[2]_PORT_A_write_enable_reg, KB1_q_a[2]_PORT_B_write_enable_reg, , , KB1_q_a[2]_clock_0, KB1_q_a[2]_clock_1, , , , );
KB1_q_a[2]_PORT_A_data_out_reg = DFFE(KB1_q_a[2]_PORT_A_data_out, KB1_q_a[2]_clock_0, , , );
KB1_q_a[2] = KB1_q_a[2]_PORT_A_data_out_reg[0];

--KB1_q_b[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_b[2]
KB1_q_b[2]_PORT_A_data_in = VCC;
KB1_q_b[2]_PORT_A_data_in_reg = DFFE(KB1_q_b[2]_PORT_A_data_in, KB1_q_b[2]_clock_0, , , );
KB1_q_b[2]_PORT_B_data_in = LB1_ram_rom_data_reg[2];
KB1_q_b[2]_PORT_B_data_in_reg = DFFE(KB1_q_b[2]_PORT_B_data_in, KB1_q_b[2]_clock_1, , , );
KB1_q_b[2]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_b[2]_PORT_A_address_reg = DFFE(KB1_q_b[2]_PORT_A_address, KB1_q_b[2]_clock_0, , , );
KB1_q_b[2]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_b[2]_PORT_B_address_reg = DFFE(KB1_q_b[2]_PORT_B_address, KB1_q_b[2]_clock_1, , , );
KB1_q_b[2]_PORT_A_write_enable = GND;
KB1_q_b[2]_PORT_A_write_enable_reg = DFFE(KB1_q_b[2]_PORT_A_write_enable, KB1_q_b[2]_clock_0, , , );
KB1_q_b[2]_PORT_B_write_enable = LB1L2;
KB1_q_b[2]_PORT_B_write_enable_reg = DFFE(KB1_q_b[2]_PORT_B_write_enable, KB1_q_b[2]_clock_1, , , );
KB1_q_b[2]_clock_0 = clk;
KB1_q_b[2]_clock_1 = A1L5;
KB1_q_b[2]_PORT_B_data_out = MEMORY(KB1_q_b[2]_PORT_A_data_in_reg, KB1_q_b[2]_PORT_B_data_in_reg, KB1_q_b[2]_PORT_A_address_reg, KB1_q_b[2]_PORT_B_address_reg, KB1_q_b[2]_PORT_A_write_enable_reg, KB1_q_b[2]_PORT_B_write_enable_reg, , , KB1_q_b[2]_clock_0, KB1_q_b[2]_clock_1, , , , );
KB1_q_b[2] = KB1_q_b[2]_PORT_B_data_out[0];


--KB1_q_a[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10, Port B Logical Depth: 512, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[1]_PORT_A_data_in = VCC;
KB1_q_a[1]_PORT_A_data_in_reg = DFFE(KB1_q_a[1]_PORT_A_data_in, KB1_q_a[1]_clock_0, , , );
KB1_q_a[1]_PORT_B_data_in = LB1_ram_rom_data_reg[1];
KB1_q_a[1]_PORT_B_data_in_reg = DFFE(KB1_q_a[1]_PORT_B_data_in, KB1_q_a[1]_clock_1, , , );
KB1_q_a[1]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[1]_PORT_A_address_reg = DFFE(KB1_q_a[1]_PORT_A_address, KB1_q_a[1]_clock_0, , , );
KB1_q_a[1]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[1]_PORT_B_address_reg = DFFE(KB1_q_a[1]_PORT_B_address, KB1_q_a[1]_clock_1, , , );
KB1_q_a[1]_PORT_A_write_enable = GND;
KB1_q_a[1]_PORT_A_write_enable_reg = DFFE(KB1_q_a[1]_PORT_A_write_enable, KB1_q_a[1]_clock_0, , , );
KB1_q_a[1]_PORT_B_write_enable = LB1L2;
KB1_q_a[1]_PORT_B_write_enable_reg = DFFE(KB1_q_a[1]_PORT_B_write_enable, KB1_q_a[1]_clock_1, , , );
KB1_q_a[1]_clock_0 = clk;
KB1_q_a[1]_clock_1 = A1L5;
KB1_q_a[1]_PORT_A_data_out = MEMORY(KB1_q_a[1]_PORT_A_data_in_reg, KB1_q_a[1]_PORT_B_data_in_reg, KB1_q_a[1]_PORT_A_address_reg, KB1_q_a[1]_PORT_B_address_reg, KB1_q_a[1]_PORT_A_write_enable_reg, KB1_q_a[1]_PORT_B_write_enable_reg, , , KB1_q_a[1]_clock_0, KB1_q_a[1]_clock_1, , , , );
KB1_q_a[1]_PORT_A_data_out_reg = DFFE(KB1_q_a[1]_PORT_A_data_out, KB1_q_a[1]_clock_0, , , );
KB1_q_a[1] = KB1_q_a[1]_PORT_A_data_out_reg[0];

--KB1_q_b[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_b[1]
KB1_q_b[1]_PORT_A_data_in = VCC;
KB1_q_b[1]_PORT_A_data_in_reg = DFFE(KB1_q_b[1]_PORT_A_data_in, KB1_q_b[1]_clock_0, , , );
KB1_q_b[1]_PORT_B_data_in = LB1_ram_rom_data_reg[1];
KB1_q_b[1]_PORT_B_data_in_reg = DFFE(KB1_q_b[1]_PORT_B_data_in, KB1_q_b[1]_clock_1, , , );
KB1_q_b[1]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_b[1]_PORT_A_address_reg = DFFE(KB1_q_b[1]_PORT_A_address, KB1_q_b[1]_clock_0, , , );
KB1_q_b[1]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_b[1]_PORT_B_address_reg = DFFE(KB1_q_b[1]_PORT_B_address, KB1_q_b[1]_clock_1, , , );
KB1_q_b[1]_PORT_A_write_enable = GND;
KB1_q_b[1]_PORT_A_write_enable_reg = DFFE(KB1_q_b[1]_PORT_A_write_enable, KB1_q_b[1]_clock_0, , , );
KB1_q_b[1]_PORT_B_write_enable = LB1L2;
KB1_q_b[1]_PORT_B_write_enable_reg = DFFE(KB1_q_b[1]_PORT_B_write_enable, KB1_q_b[1]_clock_1, , , );
KB1_q_b[1]_clock_0 = clk;
KB1_q_b[1]_clock_1 = A1L5;
KB1_q_b[1]_PORT_B_data_out = MEMORY(KB1_q_b[1]_PORT_A_data_in_reg, KB1_q_b[1]_PORT_B_data_in_reg, KB1_q_b[1]_PORT_A_address_reg, KB1_q_b[1]_PORT_B_address_reg, KB1_q_b[1]_PORT_A_write_enable_reg, KB1_q_b[1]_PORT_B_write_enable_reg, , , KB1_q_b[1]_clock_0, KB1_q_b[1]_clock_1, , , , );
KB1_q_b[1] = KB1_q_b[1]_PORT_B_data_out[0];


--KB1_q_a[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 1, Port B Depth: 512, Port B Width: 1
--Port A Logical Depth: 512, Port A Logical Width: 10, Port B Logical Depth: 512, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[0]_PORT_A_data_in = VCC;
KB1_q_a[0]_PORT_A_data_in_reg = DFFE(KB1_q_a[0]_PORT_A_data_in, KB1_q_a[0]_clock_0, , , );
KB1_q_a[0]_PORT_B_data_in = LB1_ram_rom_data_reg[0];
KB1_q_a[0]_PORT_B_data_in_reg = DFFE(KB1_q_a[0]_PORT_B_data_in, KB1_q_a[0]_clock_1, , , );
KB1_q_a[0]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[0]_PORT_A_address_reg = DFFE(KB1_q_a[0]_PORT_A_address, KB1_q_a[0]_clock_0, , , );
KB1_q_a[0]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[0]_PORT_B_address_reg = DFFE(KB1_q_a[0]_PORT_B_address, KB1_q_a[0]_clock_1, , , );
KB1_q_a[0]_PORT_A_write_enable = GND;
KB1_q_a[0]_PORT_A_write_enable_reg = DFFE(KB1_q_a[0]_PORT_A_write_enable, KB1_q_a[0]_clock_0, , , );
KB1_q_a[0]_PORT_B_write_enable = LB1L2;
KB1_q_a[0]_PORT_B_write_enable_reg = DFFE(KB1_q_a[0]_PORT_B_write_enable, KB1_q_a[0]_clock_1, , , );
KB1_q_a[0]_clock_0 = clk;
KB1_q_a[0]_clock_1 = A1L5;
KB1_q_a[0]_PORT_A_data_out = MEMORY(KB1_q_a[0]_PORT_A_data_in_reg, KB1_q_a[0]_PORT_B_data_in_reg, KB1_q_a[0]_PORT_A_address_reg, KB1_q_a[0]_PORT_B_address_reg, KB1_q_a[0]_PORT_A_write_enable_reg, KB1_q_a[0]_PORT_B_write_enable_reg, , , KB1_q_a[0]_clock_0, KB1_q_a[0]_clock_1, , , , );
KB1_q_a[0]_PORT_A_data_out_reg = DFFE(KB1_q_a[0]_PORT_A_data_out, KB1_q_a[0]_clock_0, , , );
KB1_q_a[0] = KB1_q_a[0]_PORT_A_data_out_reg[0];

--KB1_q_b[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_b[0]
KB1_q_b[0]_PORT_A_data_in = VCC;
KB1_q_b[0]_PORT_A_data_in_reg = DFFE(KB1_q_b[0]_PORT_A_data_in, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_data_in = LB1_ram_rom_data_reg[0];
KB1_q_b[0]_PORT_B_data_in_reg = DFFE(KB1_q_b[0]_PORT_B_data_in, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_b[0]_PORT_A_address_reg = DFFE(KB1_q_b[0]_PORT_A_address, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_b[0]_PORT_B_address_reg = DFFE(KB1_q_b[0]_PORT_B_address, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_PORT_A_write_enable = GND;
KB1_q_b[0]_PORT_A_write_enable_reg = DFFE(KB1_q_b[0]_PORT_A_write_enable, KB1_q_b[0]_clock_0, , , );
KB1_q_b[0]_PORT_B_write_enable = LB1L2;
KB1_q_b[0]_PORT_B_write_enable_reg = DFFE(KB1_q_b[0]_PORT_B_write_enable, KB1_q_b[0]_clock_1, , , );
KB1_q_b[0]_clock_0 = clk;
KB1_q_b[0]_clock_1 = A1L5;
KB1_q_b[0]_PORT_B_data_out = MEMORY(KB1_q_b[0]_PORT_A_data_in_reg, KB1_q_b[0]_PORT_B_data_in_reg, KB1_q_b[0]_PORT_A_address_reg, KB1_q_b[0]_PORT_B_address_reg, KB1_q_b[0]_PORT_A_write_enable_reg, KB1_q_b[0]_PORT_B_write_enable_reg, , , KB1_q_b[0]_clock_0, KB1_q_b[0]_clock_1, , , , );
KB1_q_b[0] = KB1_q_b[0]_PORT_B_data_out[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !H1_hub_tdo);