nco_bb.v

来自「DDs直接数字频率合成器的源代码」· Verilog 代码 · 共 42 行

// Generated by NCO 2.2.0 [Altera, IP Toolbench v1.2.5 build28]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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// Copyright (C) 1991-2006 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
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module nco (
	phi_inc_i,
	clk,
	reset,
	clken,
	fsin_o,
	fcos_o,
	data_ready);

	input	[31:0]	phi_inc_i;
	input		clk;
	input		reset;
	input		clken;
	output	[17:0]	fsin_o;
	output	[17:0]	fcos_o;
	output		data_ready;
endmodule