dds51.tan.summary

DDs直接数字频率合成器的源代码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.082 ns
From           : altera_internal_jtag
To             : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:name_gen:info_rom_sr|WORD_SR[3]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.585 ns
From           : lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[4]
To             : q_out[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.659 ns
From           : altera_internal_jtag
To             : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[26]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : -0.969 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[0]
To             : AddrLock:inst3|ADDRLOCK[29]
From Clock     : DPLL:inst4|altpll:altpll_component|_clk0
To Clock       : clk
Failed Paths   : 132

Type           : Clock Setup: 'DPLL:inst4|altpll:altpll_component|_clk0'
Slack          : 6.638 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : AddrLock:inst3|ADDRLOCK[19]
To             : lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node|sout_node[13]
From Clock     : clk
To Clock       : DPLL:inst4|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 80.80 MHz ( period = 12.376 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:2:IRF|Q[2]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : 0.873 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1|holdff
To             : sld_signaltap:auto_signaltap_0|acq_data_in_pipe_reg[2][2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'DPLL:inst4|altpll:altpll_component|_clk0'
Slack          : 3.623 ns
Required Time  : 80.00 MHz ( period = 12.500 ns )
Actual Time    : N/A
From           : AddrLock:inst3|ADDRLOCK[1]
To             : lpm_add_pharse:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[1]
From Clock     : clk
To Clock       : DPLL:inst4|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 132

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