dds51.fit.eqn

DDs直接数字频率合成器的源代码

LB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_reg[2], KB1_q_b[1], LB1L11, VCC, LB1L53);


--LB1_ram_rom_data_reg[0] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] at LC_X15_Y10_N7
--operation mode is normal

LB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, LB1_ram_rom_data_reg[1], LB1L11, KB1_q_b[0], VCC, LB1L53);


--H1_hub_tdo is sld_hub:sld_hub_inst|hub_tdo at LC_X20_Y7_N2
--operation mode is normal

H1_hub_tdo = AMPP_FUNCTION(!A1L5, H1L21, H1L15, H1L24, H1L18, !WB1_state[8]);


--WB1_state[4] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[4] at LC_X19_Y7_N0
--operation mode is normal

WB1_state[4] = AMPP_FUNCTION(A1L5, WB1_state[7], WB1_state[3], WB1_state[4], VCC, A1L7);


--WB1_state[3] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[3] at LC_X19_Y7_N9
--operation mode is normal

WB1_state[3] = AMPP_FUNCTION(A1L5, WB1_state[2], A1L7, VCC);


--UB9_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2] at LC_X20_Y8_N4
--operation mode is normal

UB9_Q[2] = AMPP_FUNCTION(A1L5, UB3_Q[2], H1_CLRN_SIGNAL, H1L8);


--UB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] at LC_X17_Y9_N7
--operation mode is normal

UB3_Q[2] = AMPP_FUNCTION(A1L5, M1L4, H1L34, UB3L3, UB3_Q[3], H1_CLRN_SIGNAL, UB3L4);


--H1_CLRN_SIGNAL is sld_hub:sld_hub_inst|CLRN_SIGNAL at LC_X19_Y6_N0
--operation mode is normal

H1_CLRN_SIGNAL = AMPP_FUNCTION(A1L5, UB1_Q[0], WB1_state[1], VCC);


--H1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q at LC_X21_Y8_N4
--operation mode is normal

H1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, WB1_state[4], H1_OK_TO_UPDATE_IR_Q, WB1_state[8], H1_jtag_debug_mode_usr1, VCC);


--H1L9 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~27 at LC_X18_Y9_N5
--operation mode is normal

H1L9 = AMPP_FUNCTION(H1_OK_TO_UPDATE_IR_Q, WB1_state[5]);


--UB11_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] at LC_X20_Y10_N4
--operation mode is normal

UB11_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, UB3_Q[8], VCC, H1L27);


--XB1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2] at LC_X20_Y9_N6
--operation mode is normal

XB1_dffe1a[2] = AMPP_FUNCTION(A1L5, UB3_Q[3], UB3_Q[1], UB3_Q[2], H1L41, H1_CLRN_SIGNAL, H1L5);


--H1L28 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~179 at LC_X19_Y9_N9
--operation mode is normal

H1L28 = AMPP_FUNCTION(XB1_dffe1a[2], UB11_Q[0]);


--H1L29 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~180 at LC_X19_Y7_N6
--operation mode is normal

H1L29 = AMPP_FUNCTION(H1L9, H1L28, UB2_Q[0], UB10_Q[0]);


--UB3_Q[8] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[8] at LC_X18_Y10_N4
--operation mode is normal

UB3_Q[8] = AMPP_FUNCTION(A1L5, altera_internal_jtag, H1_CLRN_SIGNAL, WB1_state[4], H1L37);


--H1L27 is sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 at LC_X19_Y9_N2
--operation mode is normal

H1L27 = AMPP_FUNCTION(H1_jtag_debug_mode_usr1, H1_OK_TO_UPDATE_IR_Q, WB1_state[4], A1L7);


--H1_jtag_debug_mode_usr0 is sld_hub:sld_hub_inst|jtag_debug_mode_usr0 at LC_X19_Y6_N8
--operation mode is normal

H1_jtag_debug_mode_usr0 = AMPP_FUNCTION(A1L5, A1L26, A1L27, Q5_dffs[0], Q5_dffs[1], WB1_state[0], WB1_state[12]);


--H1L41 is sld_hub:sld_hub_inst|jtag_debug_mode~2 at LC_X20_Y9_N1
--operation mode is normal

H1L41 = AMPP_FUNCTION(H1_jtag_debug_mode_usr0, H1_jtag_debug_mode_usr1);


--WB1_state[12] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[12] at LC_X20_Y6_N2
--operation mode is normal

WB1_state[12] = AMPP_FUNCTION(A1L5, WB1_state[10], WB1_state[11], VCC, !A1L7);


--WB1_state[2] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[2] at LC_X20_Y6_N9
--operation mode is normal

WB1_state[2] = AMPP_FUNCTION(A1L5, WB1_state[8], WB1_state[1], WB1_state[15], VCC, !A1L7);


--H1L42 is sld_hub:sld_hub_inst|jtag_debug_mode~171 at LC_X20_Y6_N8
--operation mode is normal

H1L42 = AMPP_FUNCTION(WB1_state[12], WB1_state[2], A1L7);


--WB1_state[15] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[15] at LC_X20_Y6_N6
--operation mode is normal

WB1_state[15] = AMPP_FUNCTION(A1L5, WB1_state[14], WB1_state[12], VCC, !A1L7);


--WB1_state[0] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] at LC_X19_Y6_N2
--operation mode is normal

WB1_state[0] = AMPP_FUNCTION(A1L5, WB1_state[0], A1L7, WB1_state[9], WB1L19, VCC);


--XB1_dffe1a[1] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[1] at LC_X20_Y9_N9
--operation mode is normal

XB1_dffe1a[1] = AMPP_FUNCTION(A1L5, UB3_Q[3], UB3_Q[1], UB3_Q[2], H1L41, H1_CLRN_SIGNAL, H1L5);


--WB1_state[8] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[8] at LC_X19_Y9_N6
--operation mode is normal

WB1_state[8] = AMPP_FUNCTION(A1L5, WB1_state[5], WB1_state[7], VCC, !A1L7);


--H1L1 is sld_hub:sld_hub_inst|BROADCAST_ENA~28 at LC_X19_Y9_N7
--operation mode is normal

H1L1 = AMPP_FUNCTION(XB1_dffe1a[2], H1_OK_TO_UPDATE_IR_Q, WB1_state[8], XB1_dffe1a[1]);


--Q5_dffs[1] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[1] at LC_X19_Y5_N9
--operation mode is normal

Q5_dffs[1] = AMPP_FUNCTION(A1L5, Q5_dffs[2], WB1_state[0], WB1_state[11]);


--Q5_dffs[8] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[8] at LC_X19_Y5_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[8] = AMPP_FUNCTION(A1L5, Q5_dffs[9], WB1_state[0], GND, WB1_state[11]);


--Q5_dffs[7] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[7] at LC_X19_Y5_N6
--operation mode is normal

Q5_dffs[7] = AMPP_FUNCTION(A1L5, Q5_dffs[8], WB1_state[0], WB1_state[11]);


--Q5_dffs[6] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[6] at LC_X19_Y5_N7
--operation mode is normal

Q5_dffs[6] = AMPP_FUNCTION(A1L5, Q5_dffs[7], WB1_state[0], WB1_state[11]);


--A1L26 is rtl~101 at LC_X19_Y5_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[9]_qfbk = Q5_dffs[9];
A1L26 = !Q5_dffs[6] & !Q5_dffs[8] & !Q5_dffs[9]_qfbk & !Q5_dffs[7];

--Q5_dffs[9] is sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9] at LC_X19_Y5_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

Q5_dffs[9] = AMPP_FUNCTION(A1L5, altera_internal_jtag, WB1_state[0], GND, WB1_state[11]);


--Q