dds51.fit.eqn

DDs直接数字频率合成器的源代码

-- Copyright (C) 1991-2005 Altera Corporation
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-- and other software and tools, and its AMPP partner logic 
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-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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--KB1_q_a[9] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[9] at M4K_X13_Y10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 512, Port A Width: 9, Port B Depth: 512, Port B Width: 9
--Port A Logical Depth: 512, Port A Logical Width: 10, Port B Logical Depth: 512, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9] = KB1_q_a[9]_PORT_A_data_out_reg[0];

--KB1_q_b[9] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_b[9] at M4K_X13_Y10
KB1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_b[9]_PORT_A_data_in_reg = DFFE(KB1_q_b[9]_PORT_A_data_in, KB1_q_b[9]_clock_0, , , );
KB1_q_b[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_b[9]_PORT_B_data_in_reg = DFFE(KB1_q_b[9]_PORT_B_data_in, KB1_q_b[9]_clock_1, , , );
KB1_q_b[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_b[9]_PORT_A_address_reg = DFFE(KB1_q_b[9]_PORT_A_address, KB1_q_b[9]_clock_0, , , );
KB1_q_b[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_b[9]_PORT_B_address_reg = DFFE(KB1_q_b[9]_PORT_B_address, KB1_q_b[9]_clock_1, , , );
KB1_q_b[9]_PORT_A_write_enable = GND;
KB1_q_b[9]_PORT_A_write_enable_reg = DFFE(KB1_q_b[9]_PORT_A_write_enable, KB1_q_b[9]_clock_0, , , );
KB1_q_b[9]_PORT_B_write_enable = LB1L2;
KB1_q_b[9]_PORT_B_write_enable_reg = DFFE(KB1_q_b[9]_PORT_B_write_enable, KB1_q_b[9]_clock_1, , , );
KB1_q_b[9]_clock_0 = GLOBAL(clk);
KB1_q_b[9]_clock_1 = GLOBAL(A1L5);
KB1_q_b[9]_PORT_B_data_out = MEMORY(KB1_q_b[9]_PORT_A_data_in_reg, KB1_q_b[9]_PORT_B_data_in_reg, KB1_q_b[9]_PORT_A_address_reg, KB1_q_b[9]_PORT_B_address_reg, KB1_q_b[9]_PORT_A_write_enable_reg, KB1_q_b[9]_PORT_B_write_enable_reg, , , KB1_q_b[9]_clock_0, KB1_q_b[9]_clock_1, , , , );
KB1_q_b[9] = KB1_q_b[9]_PORT_B_data_out[0];

--KB1_q_a[1] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[1] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[1] = KB1_q_a[9]_PORT_A_data_out_reg[8];

--KB1_q_a[2] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[2] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[2] = KB1_q_a[9]_PORT_A_data_out_reg[7];

--KB1_q_a[3] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[3] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[3] = KB1_q_a[9]_PORT_A_data_out_reg[6];

--KB1_q_a[4] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[4] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[4] = KB1_q_a[9]_PORT_A_data_out_reg[5];

--KB1_q_a[5] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[5] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[5] = KB1_q_a[9]_PORT_A_data_out_reg[4];

--KB1_q_a[6] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[6] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[6] = KB1_q_a[9]_PORT_A_data_out_reg[3];

--KB1_q_a[7] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[7] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;
KB1_q_a[9]_PORT_A_write_enable_reg = DFFE(KB1_q_a[9]_PORT_A_write_enable, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_write_enable = LB1L2;
KB1_q_a[9]_PORT_B_write_enable_reg = DFFE(KB1_q_a[9]_PORT_B_write_enable, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_clock_0 = GLOBAL(clk);
KB1_q_a[9]_clock_1 = GLOBAL(A1L5);
KB1_q_a[9]_PORT_A_data_out = MEMORY(KB1_q_a[9]_PORT_A_data_in_reg, KB1_q_a[9]_PORT_B_data_in_reg, KB1_q_a[9]_PORT_A_address_reg, KB1_q_a[9]_PORT_B_address_reg, KB1_q_a[9]_PORT_A_write_enable_reg, KB1_q_a[9]_PORT_B_write_enable_reg, , , KB1_q_a[9]_clock_0, KB1_q_a[9]_clock_1, , , , );
KB1_q_a[9]_PORT_A_data_out_reg = DFFE(KB1_q_a[9]_PORT_A_data_out, KB1_q_a[9]_clock_0, , , );
KB1_q_a[7] = KB1_q_a[9]_PORT_A_data_out_reg[2];

--KB1_q_a[8] is lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_p0u:auto_generated|altsyncram_6r92:altsyncram1|q_a[8] at M4K_X13_Y10
KB1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC, VCC);
KB1_q_a[9]_PORT_A_data_in_reg = DFFE(KB1_q_a[9]_PORT_A_data_in, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_data_in = BUS(LB1_ram_rom_data_reg[9], LB1_ram_rom_data_reg[8], LB1_ram_rom_data_reg[7], LB1_ram_rom_data_reg[6], LB1_ram_rom_data_reg[5], LB1_ram_rom_data_reg[4], LB1_ram_rom_data_reg[3], LB1_ram_rom_data_reg[2], LB1_ram_rom_data_reg[1]);
KB1_q_a[9]_PORT_B_data_in_reg = DFFE(KB1_q_a[9]_PORT_B_data_in, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_address = BUS(F1_ADDRLOCK[23], F1_ADDRLOCK[24], F1_ADDRLOCK[25], F1_ADDRLOCK[26], F1_ADDRLOCK[27], F1_ADDRLOCK[28], F1_ADDRLOCK[29], F1_ADDRLOCK[30], F1_ADDROUT[8]);
KB1_q_a[9]_PORT_A_address_reg = DFFE(KB1_q_a[9]_PORT_A_address, KB1_q_a[9]_clock_0, , , );
KB1_q_a[9]_PORT_B_address = BUS(LB1_ram_rom_addr_reg[0], LB1_ram_rom_addr_reg[1], LB1_ram_rom_addr_reg[2], LB1_ram_rom_addr_reg[3], LB1_ram_rom_addr_reg[4], LB1_ram_rom_addr_reg[5], LB1_ram_rom_addr_reg[6], LB1_ram_rom_addr_reg[7], LB1_ram_rom_addr_reg[8]);
KB1_q_a[9]_PORT_B_address_reg = DFFE(KB1_q_a[9]_PORT_B_address, KB1_q_a[9]_clock_1, , , );
KB1_q_a[9]_PORT_A_write_enable = GND;