mymul.vhd

这是一段用VHDL语言编写的程序 用FPGA实现模糊控制器

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY mymul IS
	PORT
	(
		dataa		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		datab		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		result		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
END mymul;


ARCHITECTURE SYN OF mymul IS

	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (15 DOWNTO 0);



	COMPONENT lpm_mult
	GENERIC (
		lpm_widtha		: NATURAL;
		lpm_widthb		: NATURAL;
		lpm_widthp		: NATURAL;
		lpm_widths		: NATURAL;
		input_b_is_constant		: STRING;
		lpm_representation		: STRING;
		use_eab		: STRING
	);
	PORT (
			dataa	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			datab	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
			result	: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
	END COMPONENT;

BEGIN
	result    <= sub_wire0(15 DOWNTO 0);

	lpm_mult_component : lpm_mult
	GENERIC MAP (
		LPM_WIDTHA => 8,
		LPM_WIDTHB => 8,
		LPM_WIDTHP => 16,
		LPM_WIDTHS => 16,
		INPUT_B_IS_CONSTANT => "NO",
		LPM_REPRESENTATION => "UNSIGNED",
		USE_EAB => "OFF"
	)
	PORT MAP (
		dataa => dataa,
		datab => datab,
		result => sub_wire0
	);



END SYN;