vhdlsourcecodeforadconverterdac8840.vhd

一个数模转换器的vhdl源码 一个数模转换器的vhdl源码

--------------------------------------------------------------------------------
--  File Name: dac8840.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2002 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    02 Jun 28   Initial release
-- 
--  This model must be compiled without VITAL compliance checking
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CONVERTER_VHDL
--  Technology: MIXED
--  Part:       DAC8840
-- 
--  Description: 8-Bit, Octal, 4-Quandrant Multiplying, TrimDAC
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY dac8840 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_SDI                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_LD                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_PRENeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_SDO              : VitalDelayType01 := UnitDelay01;
        -- tsetup values: setup times
        tsetup_SDI_CLK           : VitalDelayType := UnitDelay;
        tsetup_LD_CLK            : VitalDelayType := UnitDelay;
        tsetup_CLK_LD            : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_SDI_CLK            : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge          : VitalDelayType := UnitDelay;
        tpw_CLK_negedge          : VitalDelayType := UnitDelay;
        tpw_LD_posedge           : VitalDelayType := UnitDelay;
        tpw_PRENeg_negedge       : VitalDelayType := UnitDelay;

        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        INA             : IN    real := 0.0;
        INB             : IN    real := 0.0;
        INC             : IN    real := 0.0;
        IND             : IN    real := 0.0;
        INE             : IN    real := 0.0;
        INF             : IN    real := 0.0;
        ING             : IN    real := 0.0;
        INH             : IN    real := 0.0;
        SDI             : IN    std_ulogic := 'U';
        SDO             : OUT   std_ulogic := 'U';
        LD              : IN    std_ulogic := 'U';
        OUTA            : OUT   real := 0.0;
        OUTB            : OUT   real := 0.0;
        OUTC            : OUT   real := 0.0;
        OUTD            : OUT   real := 0.0;
        OUTE            : OUT   real := 0.0;
        OUTF            : OUT   real := 0.0;
        OUTG            : OUT   real := 0.0;
        OUTH            : OUT   real := 0.0;
        CLK             : IN    std_ulogic := 'U';
        PRENeg          : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of dac8840 : ENTITY IS TRUE;
END dac8840;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of dac8840 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    TYPE dacval_type IS ARRAY (8 DOWNTO 1) OF NATURAL RANGE 0 TO 255;

    SIGNAL SDI_ipd             : std_ulogic := 'U';
    SIGNAL LD_ipd              : std_ulogic := 'U';
    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL PRENeg_ipd          : std_ulogic := 'U';
    SIGNAL UPDATE              : std_ulogic := '0';
    SIGNAL dacval              : dacval_type;

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_9 : VitalWireDelay (SDI_ipd, SDI, tipd_SDI);
        w_11 : VitalWireDelay (LD_ipd, LD, tipd_LD);
        w_23 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_24 : VitalWireDelay (PRENeg_ipd, PRENeg, tipd_PRENeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Behavior Process
    ----------------------------------------------------------------------------
    digital : PROCESS (SDI_ipd, PRENeg_ipd, CLK_ipd, LD_ipd)

        -- Timing Check Variables
        VARIABLE Tviol_SDI_CLK    : X01 := '0';
        VARIABLE TD_SDI_CLK       : VitalTimingDataType;

        VARIABLE Tviol_LD_CLK     : X01 := '0';
        VARIABLE TD_LD_CLK        : VitalTimingDataType;

        VARIABLE Tviol_CLK_LD     : X01 := '0';
        VARIABLE TD_CLK_LD        : VitalTimingDataType;

        VARIABLE PD_CLK          : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_CLK       : X01 := '0';

        VARIABLE PD_LD           : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_LD        : X01 := '0';

        VARIABLE PD_PRENeg       : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_PRENeg    : X01 := '0';

        VARIABLE Violation      : X01 := '0';

        TYPE dacreg_type IS ARRAY (8 DOWNTO 1) OF std_logic_vector(7 DOWNTO 0);
        VARIABLE inreg      : std_logic_vector(11 DOWNTO 0);
        VARIABLE addr       : NATURAL RANGE 0 TO 15;
        VARIABLE dacreg     : dacreg_type;
        VARIABLE LD_nwv     : X01;
        VARIABLE PRENeg_nwv : X01;
        VARIABLE CLK_nwv    : X01;
        VARIABLE SDI_nwv    : X01;

        VARIABLE SDO_zd   : std_logic;

        -- Output Glitch Detection Variables
        VARIABLE SDO_GlitchData  : VitalGlitchDataType;

    BEGIN

       LD_nwv := to_X01(LD_ipd);
       PRENeg_nwv := to_X01(PRENeg_ipd);
       CLK_nwv := to_X01(CLK_ipd);
       SDI_nwv := to_X01(SDI_ipd);

        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN
            VitalSetupHoldCheck (
                TestSignal      => SDI_ipd,
                TestSignalName  => "SDI",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK",
                SetupHigh       => tsetup_SDI_CLK,
                SetupLow        => tsetup_SDI_CLK,
                HoldHigh        => thold_SDI_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & "/dac8840",
                TimingData      => TD_SDI_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_SDI_CLK
            );

            VitalSetupHoldCheck (
                TestSignal      => LD_ipd,
                TestSignalName  => "LD",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK",
                SetupHigh       => tsetup_LD_CLK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & "/dac8840",
                TimingData      => TD_LD_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LD_CLK
            );

            VitalSetupHoldCheck (
                TestSignal      => CLK_ipd,
                TestSignalName  => "CLK",
                RefSignal       => LD_ipd,
                RefSignalName   => "LD",
                SetupHigh       => tsetup_CLK_LD,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & "/dac8840",
                TimingData      => TD_CLK_LD,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CLK_LD
            );

            VitalPeriodPulseCheck (
                TestSignal      => CLK_ipd,
                TestSignalName  => "CLK_ipd",
                PulseWidthHigh  => tpw_CLK_posedge,
                PulseWidthLow   => tpw_CLK_negedge,
                HeaderMsg       => InstancePath & "/dac8840",
                CheckEnabled    => TRUE,
                PeriodData      => PD_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => LD_ipd,
                TestSignalName  => "LD",
                PulseWidthHigh  => tpw_LD_posedge,
                HeaderMsg       => InstancePath & "/dac8840",
                CheckEnabled    => TRUE,
                PeriodData      => PD_LD,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_LD
            );

            VitalPeriodPulseCheck (
                TestSignal      => PRENeg_ipd,
                TestSignalName  => "PRENeg",
                PulseWidthLow   => tpw_PRENeg_negedge,
                HeaderMsg       => InstancePath & "/dac8840",
                CheckEnabled    => TRUE,
                PeriodData      => PD_PRENeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_PRENeg
            );

            Violation := Tviol_SDI_CLK OR Tviol_LD_CLK OR Tviol_CLK_LD OR
                         Pviol_CLK OR Pviol_LD OR Pviol_PRENeg;

        END IF;
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        IF PRENeg_nwv = '0' AND LD_nwv = '0' THEN  -- preset
            dacreg := (others => "00000000");
            dacval <= (others => 0);
            UPDATE <= not UPDATE;
        ELSIF CLK_nwv = '0' AND LD_nwv = '1' THEN  -- load
            addr := to_nat(inreg(11 DOWNTO 8));
            IF addr > 0 AND addr < 9 THEN
                dacreg(addr) := inreg(7 DOWNTO 0);
                dacval(addr) <= to_nat(dacreg(addr));
            END IF;
            UPDATE <= not UPDATE;
        ELSIF rising_edge(CLK_ipd) AND LD_nwv = '0' AND PRENeg_nwv = '1' THEN
            SDO_zd := inreg(11);
            FOR i IN 11 DOWNTO 1 LOOP
                inreg(i) := inreg(i - 1);
            END LOOP;
            inreg(0) := SDI_nwv;
        END IF;
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => SDO,
            OutSignalName   => "SDO",
            OutTemp         => SDO_zd,
            GlitchData      => SDO_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => CLK_ipd'LAST_EVENT,
                      PathDelay         => tpd_CLK_SDO,
                      PathCondition     => TRUE)
            )
        );

    END PROCESS digital;

    dacA : PROCESS (INA, UPDATE)

    BEGIN

        OUTA <= ((REAL(dacval(1))/128.0) - 1.0) * INA;

    END PROCESS dacA;

    dacB : PROCESS (INB, UPDATE)

    BEGIN

        OUTB <= ((REAL(dacval(2))/128.0) - 1.0) * INB;

    END PROCESS dacB;

    dacC : PROCESS (INC, UPDATE)

    BEGIN

        OUTC <= ((REAL(dacval(3))/128.0) - 1.0) * INC;

    END PROCESS dacC;

    dacD : PROCESS (IND, UPDATE)

    BEGIN

        OUTD <= ((REAL(dacval(4))/128.0) - 1.0) * IND;

    END PROCESS dacD;

    dacE : PROCESS (INE, UPDATE)

    BEGIN

        OUTE <= ((REAL(dacval(5))/128.0) - 1.0) * INE;

    END PROCESS dacE;

    dacF : PROCESS (INF, UPDATE)

    BEGIN

        OUTF <= ((REAL(dacval(6))/128.0) - 1.0) * INF;

    END PROCESS dacF;

    dacG : PROCESS (ING, UPDATE)

    BEGIN

        OUTG <= ((REAL(dacval(7))/128.0) - 1.0) * ING;

    END PROCESS dacG;

    dacH : PROCESS (INH, UPDATE)

    BEGIN

        OUTH <= ((REAL(dacval(8))/128.0) - 1.0) * INH;

    END PROCESS dacH;

END vhdl_behavioral;