vhdlsourcecodeforadconverterak4380.vhd

一个adc的vhdl源码之七 一个adc的vhdl源码之七(第一个压缩包含5个)

--------------------------------------------------------------------------------
--  File Name: ak4380.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2003 Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  MODIFICATION HISTORY:
--
--  version: | author:   | mod date: | changes made:
--   V1.0    M.Radmanovic  03 Aug 14    Initial release
--
-- This model must be compiled without VITAL compliance checking
--
-- At the power-down mode the value 0.0 is assigned to analog outputs
-- to represent high impedance
--
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
--
--  Library: CONVERTER_VHDL
--  Technology: MIXED
--  Part: AK4380
--  Description: 100 dB 24Bit 96kHz 2ch DAC
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
 ENTITY ak4380 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_MCLK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_BICK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_SDTI                : VitalDelayType01 := VitalZeroDelay01;
        tipd_LRCK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_PDNNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_SP                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_CSN                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_CCLK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_CDTI                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        -- tsetup values: setup times
        tsetup_SDTI_BICK              : VitalDelayType := UnitDelay;
        tsetup_LRCK_BICK              : VitalDelayType := UnitDelay;
        tsetup_CDTI_CCLK              : VitalDelayType := UnitDelay;
        tsetup_CSN_CCLK               : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_SDTI_BICK               : VitalDelayType := UnitDelay;
        thold_LRCK_BICK               : VitalDelayType := UnitDelay;
        thold_CDTI_CCLK               : VitalDelayType := UnitDelay;
        thold_CSN_CCLK                : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CCLK_posedge              : VitalDelayType := UnitDelay;
        tpw_CCLK_negedge              : VitalDelayType := UnitDelay;
        tpw_BICK_posedge              : VitalDelayType := UnitDelay;
        tpw_BICK_negedge              : VitalDelayType := UnitDelay;
        tpw_CSN_posedge               : VitalDelayType := UnitDelay;
        tpw_PDNNeg_negedge            : VitalDelayType := UnitDelay;
        -- tperiod min (calculated as 1/max freq)
        tperiod_MCLK                  : VitalDelayType := UnitDelay;
        tperiod_LRCK                  : VitalDelayType := UnitDelay;
        tperiod_CCLK                  : VitalDelayType := UnitDelay;
        tperiod_BICKN                 : VitalDelayType := UnitDelay;
        tperiod_BICKD                 : VitalDelayType := UnitDelay;
        -- analog generics:
        Vref                : real; --value of Vref input In Volts
        VCOM                : real; --Voltage pin Vdd/2
        -- generic control parameters
        InstancePath        : STRING  := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN := DefaultTimingChecks;
        MsgOn               : BOOLEAN := DefaultMsgOn;
        XOn                 : BOOLEAN := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING  := DefaultTimingModel
    );
    PORT (
        MCLK             : IN    std_ulogic := 'U';
        BICK             : IN    std_ulogic := 'U';
        SDTI             : IN    std_ulogic := 'U';
        LRCK             : IN    std_ulogic := 'U';
        AOUTR            : OUT   real := 0.0;-- 0.0 is used to represent Hi-Z
        AOUTL            : OUT   real := 0.0;-- 0.0 is used to represent Hi-Z
        PDNNeg           : IN    std_ulogic := 'U';
        SP               : IN    std_ulogic := 'U';
        CSN              : IN    std_ulogic := 'U';
        CCLK             : IN    std_ulogic := 'U';
        CDTI             : IN    std_ulogic := 'U';
        DZF              : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of ak4380 : ENTITY IS TRUE;
END ak4380 ;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of ak4380 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID             : STRING := "ak4380";
    CONSTANT tmaxperiod_MCLK    : TIME := 0.5 us;-- 1/min fMCLK
    CONSTANT tmaxperiod_LRCK    : TIME := 125 us;-- 1/min fs

    SIGNAL MCLK_ipd             : std_ulogic := 'U';
    SIGNAL BICK_ipd             : std_ulogic := 'U';
    SIGNAL SDTI_ipd             : std_ulogic := 'U';
    SIGNAL LRCK_ipd             : std_ulogic := 'U';
    SIGNAL PDNNeg_ipd           : std_ulogic := 'U';
    SIGNAL SP_ipd               : std_ulogic := 'U';
    SIGNAL CSN_ipd              : std_ulogic := 'U';  --SMUTE in parallel mode
    SIGNAL CCLK_ipd             : std_ulogic := 'U';  --DFS in parallel mode
    SIGNAL CDTI_ipd             : std_ulogic := 'U';  --DIF0 in parallel mode

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1  : VitalWireDelay (MCLK_ipd, MCLK, tipd_MCLK);
        w_2  : VitalWireDelay (BICK_ipd, BICK, tipd_BICK);
        w_3  : VitalWireDelay (SDTI_ipd, SDTI, tipd_SDTI);
        w_4  : VitalWireDelay (LRCK_ipd, LRCK, tipd_LRCK);
        w_7  : VitalWireDelay (PDNNeg_ipd, PDNNeg, tipd_PDNNeg);
        w_8  : VitalWireDelay (SP_ipd, SP, tipd_SP);
        w_9  : VitalWireDelay (CSN_ipd, CSN, tipd_CSN);
        w_10 : VitalWireDelay (CCLK_ipd, CCLK, tipd_CCLK);
        w_11 : VitalWireDelay (CDTI_ipd, CDTI, tipd_CDTI);

    END BLOCK;

    Behavior : BLOCK

        SIGNAL Reset                : std_ulogic := '1';
        SIGNAL RSTN                 : std_ulogic := '1';
        SIGNAL SMUTE                : std_ulogic := '0';
        SIGNAL Pwdn                 : std_ulogic := '1';
        SIGNAL DFS                  : std_ulogic := 'U';
        SIGNAL MOff                 : BOOLEAN := true;
        SIGNAL LROff                : BOOLEAN := true;
        SIGNAL Powerup              : BOOLEAN := true;

        SIGNAL ControlM             : std_ulogic := '0';
        SIGNAL ControlLR            : std_ulogic := '0';

        SIGNAL Period               : TIME := 0 ns;
        SIGNAL AOUTR_zd19           : real := 0.0;
        SIGNAL AOUTL_zd19           : real := 0.0;

    BEGIN

    Clock: PROCESS (MCLK_ipd, LRCK_ipd, ControlM, ControlLR)

        VARIABLE TmpLRCK            : TIME := 0 ns;

    BEGIN

        IF rising_edge(ControlM) THEN
            MOff <= true;
        END IF;
        IF rising_edge(MCLK_ipd) THEN
            MOff <= false;
            ControlM <= '0', '1' AFTER tmaxperiod_MCLK;
        END IF;

         IF rising_edge(ControlLR) THEN
            LROff <= true;
        END IF;
        IF rising_edge(LRCK_ipd) THEN
            LROff <= false;
            ControlLR <= '0', '1' AFTER tmaxperiod_LRCK;
            Period <= NOW - TmpLRCK;
            TmpLRCK := NOW;
        END IF;

    END PROCESS Clock;

    PwrUp: PROCESS (PDNNeg_ipd, MOff, LROff, Pwdn)

    BEGIN

        IF rising_edge(PDNNeg_ipd) OR rising_edge(Pwdn) THEN
            IF MOff OR LROff THEN
            --AK4380 is in power down until MCLK and LRCK are input
                Powerup <= false;
            ELSE
                Powerup <= true;
            END IF;
        END IF;
        IF not(Powerup) THEN
            IF not(MOff) AND not(LROff) THEN
                Powerup <= true;
            END IF;
        END IF;

    END PROCESS PwrUp;

    ----------------------------------------------------------------------------
    -- Behavior Process
    ----------------------------------------------------------------------------
    Behavior: PROCESS (BICK_ipd, SDTI_ipd, LRCK_ipd, CSN_ipd,
                       CCLK_ipd, CDTI_ipd, SP_ipd, PDNNeg_ipd,
                       Powerup, MOff, LROff, Reset, Smute, Pwdn)

    -- Timing Check Variables
    VARIABLE Tviol_SDTI_BICK     : X01 := '0';
    VARIABLE TD_SDTI_BICK        : VitalTimingDataType;

    VARIABLE Tviol_LRCK_BICK     : X01 := '0';
    VARIABLE TD_LRCK_BICK        : VitalTimingDataType;

    VARIABLE Tviol_CDTI_CCLK     : X01 := '0';
    VARIABLE TD_CDTI_CCLK        : VitalTimingDataType;

    VARIABLE Tviol_CSN_CCLK      : X01 := '0';
    VARIABLE TD_CSN_CCLK         : VitalTimingDataType;

    VARIABLE Pviol_CCLK          :  X01 := '0';
    VARIABLE TD_CCLK             : VitalPeriodDataType := VitalPeriodDataInit;

    VARIABLE Pviol_BICKN         :  X01 := '0';
    VARIABLE TD_BICKN            : VitalPeriodDataType := VitalPeriodDataInit;

    VARIABLE Pviol_BICKD         :  X01 := '0';
    VARIABLE TD_BICKD            : VitalPeriodDataType := VitalPeriodDataInit;

    VARIABLE Pviol_CSN           :  X01 := '0';
    VARIABLE TD_CSN              : VitalPeriodDataType := VitalPeriodDataInit;

    VARIABLE Pviol_PDNNeg        :  X01 := '0';
    VARIABLE TD_PDNNeg           : VitalPeriodDataType := VitalPeriodDataInit;

    VARIABLE Pviol_LRCK          :  X01 := '0';
    VARIABLE TD_LRCK             : VitalPeriodDataType := VitalPeriodDataInit;

    VARIABLE Pviol_MCLK          :  X01 := '0';
    VARIABLE TD_MCLK             : VitalPeriodDataType := VitalPeriodDataInit;

    VARIABLE Violation           : X01 := '0';

    SUBTYPE controlreg_type IS    std_logic_vector(7 DOWNTO 0);

    VARIABLE inreg          : std_logic_vector(15 DOWNTO 0);
    VARIABLE control1       : controlreg_type := "00001111";
    VARIABLE control2       : controlreg_type := "00000010";
    VARIABLE AOUTL_zd       : REAL := 0.0;
    VARIABLE AOUTR_zd       : REAL := 0.0;
    VARIABLE AOUTR_zd1      : REAL := 0.0;
    VARIABLE AOUTR_zd2      : REAL := 0.0;
    VARIABLE AOUTR_zd3      : REAL := 0.0;
    VARIABLE AOUTR_zd4      : REAL := 0.0;
    VARIABLE AOUTR_zd5      : REAL := 0.0;
    VARIABLE AOUTR_zd6      : REAL := 0.0;
    VARIABLE AOUTR_zd7      : REAL := 0.0;
    VARIABLE AOUTR_zd8      : REAL := 0.0;
    VARIABLE AOUTR_zd9      : REAL := 0.0;
    VARIABLE AOUTR_zd10     : REAL := 0.0;
    VARIABLE AOUTR_zd11     : REAL := 0.0;
    VARIABLE AOUTR_zd12     : REAL := 0.0;
    VARIABLE AOUTR_zd13     : REAL := 0.0;
    VARIABLE AOUTR_zd14     : REAL := 0.0;
    VARIABLE AOUTR_zd15     : REAL := 0.0;
    VARIABLE AOUTR_zd16     : REAL := 0.0;
    VARIABLE AOUTR_zd17     : REAL := 0.0;
    VARIABLE AOUTR_zd18     : REAL := 0.0;
    VARIABLE AOUTL_zd1      : REAL := 0.0;
    VARIABLE AOUTL_zd2      : REAL := 0.0;
    VARIABLE AOUTL_zd3      : REAL := 0.0;
    VARIABLE AOUTL_zd4      : REAL := 0.0;
    VARIABLE AOUTL_zd5      : REAL := 0.0;
    VARIABLE AOUTL_zd6      : REAL := 0.0;
    VARIABLE AOUTL_zd7      : REAL := 0.0;
    VARIABLE AOUTL_zd8      : REAL := 0.0;
    VARIABLE AOUTL_zd9      : REAL := 0.0;
    VARIABLE AOUTL_zd10     : REAL := 0.0;
    VARIABLE AOUTL_zd11     : REAL := 0.0;
    VARIABLE AOUTL_zd12     : REAL := 0.0;
    VARIABLE AOUTL_zd13     : REAL := 0.0;
    VARIABLE AOUTL_zd14     : REAL := 0.0;
    VARIABLE AOUTL_zd15     : REAL := 0.0;
    VARIABLE AOUTL_zd16     : REAL := 0.0;
    VARIABLE AOUTL_zd17     : REAL := 0.0;
    VARIABLE AOUTL_zd18     : REAL := 0.0;

    VARIABLE LchData       : std_logic_vector(31 DOWNTO 0) := (others => '0');
    VARIABLE RchData       : std_logic_vector(31 DOWNTO 0) := (others => '0');
    VARIABLE Lchreg0       : std_logic_vector(15 DOWNTO 0) := (others => '0');
    VARIABLE Rchreg0       : std_logic_vector(15 DOWNTO 0) := (others => '0');
    VARIABLE Lchreg1       : std_logic_vector(19 DOWNTO 0) := (others => '0');
    VARIABLE Rchreg1       : std_logic_vector(19 DOWNTO 0) := (others => '0');
    VARIABLE Lchreg        : std_logic_vector(23 DOWNTO 0) := (others => '0');
    VARIABLE Rchreg        : std_logic_vector(23 DOWNTO 0) := (others => '0');
    VARIABLE TmpL          : REAL := 0.0;
    VARIABLE TmpR          : REAL := 0.0;

    VARIABLE Mode                 : NATURAL RANGE 0 TO 4 := 3;
    VARIABLE delaycnt             : NATURAL RANGE 0 TO 4;
    VARIABLE delaycnt1            : NATURAL RANGE 0 TO 3;
    VARIABLE delaycnt2            : NATURAL RANGE 0 TO 2;
    VARIABLE smutecnt             : NATURAL RANGE 0 TO 1024 := 0;
    VARIABLE dzfcnt               : NATURAL RANGE 0 TO 8192 := 0;
    VARIABLE ResetOn              : BOOLEAN := false;
    VARIABLE ResetOff             : BOOLEAN := false;
    VARIABLE SmuteOff             : BOOLEAN := false;
    VARIABLE inv                  : BOOLEAN := false;
    VARIABLE size                 : INTEGER;

    VARIABLE MCLK_nwv         : X01;
    VARIABLE BICK_nwv         : X01;
    VARIABLE SDTI_nwv         : X01;
    VARIABLE LRCK_nwv         : X01;
    VARIABLE CSN_nwv          : X01;
    VARIABLE CCLK_nwv         : X01;
    VARIABLE CDTI_nwv         : X01;
    VARIABLE SP_nwv           : X01;
    VARIABLE PDNNeg_nwv       : X01;

    BEGIN

        MCLK_nwv        := to_X01(MCLK_ipd);
        BICK_nwv        := to_X01(BICK_ipd);
        SDTI_nwv        := to_X01(SDTI_ipd);
        LRCK_nwv        := to_X01(LRCK_ipd);
        CSN_nwv         := to_X01(CSN_ipd);
        CCLK_nwv        := to_X01(CCLK_ipd);
        CDTI_nwv        := to_X01(CDTI_ipd);
        SP_nwv          := to_X01(SP_ipd);
        PDNNeg_nwv      := to_X01(PDNNeg_ipd);

        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN

            VitalSetupHoldCheck (
                TestSignal      => SDTI_ipd,
                TestSignalName  => "SDTI",
                RefSignal       => BICK_ipd,
                RefSignalName   => "BICK",
                SetupHigh       => tsetup_SDTI_BICK,
                SetupLow        => tsetup_SDTI_BICK,
                HoldHigh        => thold_SDTI_BICK,
                HoldLow         => thold_SDTI_BICK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_SDTI_BICK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_SDTI_BICK
            );

            VitalSetupHoldCheck (
                TestSignal      => LRCK_ipd,
                TestSignalName  => "LRCK",
                RefSignal       => BICK_ipd,
                RefSignalName   => "BICK",
                SetupHigh       => tsetup_LRCK_BICK,
                SetupLow        => tsetup_LRCK_BICK,
                HoldHigh        => thold_LRCK_BICK,
                HoldLow         => thold_LRCK_BICK,
                CheckEnabled    => true,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_LRCK_BICK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_LRCK_BICK
            );