vhdlsourcecodeforadconvertersadv7123.vhd

vhdl源码for模数转换器之七 vhdl源码for模数转换器之七

            IOGOut    : OUT  real := 0.0;
            IOGNegOut : OUT  real := 0.0;
            IOBOut    : OUT  real := 0.0;
            IOBNegOut : OUT  real := 0.0
        );
        PORT MAP (
            RIn(0) => R0_ipd,
            RIn(1) => R1_ipd,
            RIn(2) => R2_ipd,
            RIn(3) => R3_ipd,
            RIn(4) => R4_ipd,
            RIn(5) => R5_ipd,
            RIn(6) => R6_ipd,
            RIn(7) => R7_ipd,
            RIn(8) => R8_ipd,
            RIn(9) => R9_ipd,
            GIn(0) => G0_ipd,
            GIn(1) => G1_ipd,
            GIn(2) => G2_ipd,
            GIn(3) => G3_ipd,
            GIn(4) => G4_ipd,
            GIn(5) => G5_ipd,
            GIn(6) => G6_ipd,
            GIn(7) => G7_ipd,
            GIn(8) => G8_ipd,
            GIn(9) => G9_ipd,
            BIn(0) => B0_ipd,
            BIn(1) => B1_ipd,
            BIn(2) => B2_ipd,
            BIn(3) => B3_ipd,
            BIn(4) => B4_ipd,
            BIn(5) => B5_ipd,
            BIn(6) => B6_ipd,
            BIn(7) => B7_ipd,
            BIn(8) => B8_ipd,
            BIn(9) => B9_ipd,
            BLANKIn => BLANKNeg_ipd,
            SYNCIn => SYNCNeg_ipd,
            CLKIn => CLK_ipd,
            PSAVEIn => PSAVENeg_ipd,
            IOROut => IOR,
            IORNegOut => IORNeg,
            IOGOut => IOG,
            IOGNegOut => IOGNeg,
            IOBOut => IOB,
            IOBNegOut => IOBNeg
        );

    BEGIN
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Behavior : PROCESS (RIn, GIn, BIn, BLANKIn, SYNCIn, CLKIn, PSAVEIn)

            -- Timing Check Variables
            VARIABLE Tviol_R_CLK       : X01 := '0';
            VARIABLE TD_R_CLK          : VitalTimingDataType;

            VARIABLE Tviol_G_CLK       : X01 := '0';
            VARIABLE TD_G_CLK          : VitalTimingDataType;

            VARIABLE Tviol_B_CLK       : X01 := '0';
            VARIABLE TD_B_CLK          : VitalTimingDataType;

            VARIABLE Tviol_SYNC_CLK    : X01 := '0';
            VARIABLE TD_SYNC_CLK       : VitalTimingDataType;

            VARIABLE Tviol_BLANK_CLK   : X01 := '0';
            VARIABLE TD_BLANK_CLK      : VitalTimingDataType;

            VARIABLE Pviol_CLK     : X01 := '0';
            VARIABLE PD_CLK        : VitalPeriodDataType := VitalPeriodDataInit;

            -- Functionality Results Variables
            VARIABLE Violation  : X01 := '0';
            VARIABLE Rreg       : NATURAL := 0;
            VARIABLE Greg       : NATURAL := 0;
            VARIABLE Breg       : NATURAL := 0;
            VARIABLE IOR_zd     : REAL    := 0.0;
            VARIABLE IORNeg_zd  : REAL    := 0.0;
            VARIABLE IOG_zd     : REAL    := 0.0;
            VARIABLE IOGNeg_zd  : REAL    := 0.0;
            VARIABLE IOB_zd     : REAL    := 0.0;
            VARIABLE IOBNeg_zd  : REAL    := 0.0;

            -- No Weak Values Variables
            VARIABLE SYNC_nwv    : UX01 := 'X';
            VARIABLE BLANK_nwv   : UX01 := 'X';
            VARIABLE PSAVE_nwv   : UX01 := 'X';

        BEGIN
            SYNC_nwv    := To_UX01 (s => SYNCIn);
            BLANK_nwv   := To_UX01 (s => BLANKIn);
            PSAVE_nwv   := To_UX01 (s => PSAVEIn);

            --------------------------------------------------------------------
            -- Timing Check Section
            --------------------------------------------------------------------
            IF (TimingChecksOn) THEN

                VitalSetupHoldCheck (
                    TestSignal      => RIn,
                    TestSignalName  => "R",
                    RefSignal       => CLK,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_R0_CLK,
                    SetupLow        => tsetup_R0_CLK,
                    HoldHigh        => thold_R0_CLK,
                    HoldLow         => thold_R0_CLK,
                    CheckEnabled    => (PSAVE_nwv ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_R_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_R_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => GIn,
                    TestSignalName  => "G",
                    RefSignal       => CLK,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_R0_CLK,
                    SetupLow        => tsetup_R0_CLK,
                    HoldHigh        => thold_R0_CLK,
                    HoldLow         => thold_R0_CLK,
                    CheckEnabled    => (PSAVE_nwv ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_G_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_G_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => BIn,
                    TestSignalName  => "B",
                    RefSignal       => CLK,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_R0_CLK,
                    SetupLow        => tsetup_R0_CLK,
                    HoldHigh        => thold_R0_CLK,
                    HoldLow         => thold_R0_CLK,
                    CheckEnabled    => (PSAVE_nwv ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_B_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_B_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => SYNCIn,
                    TestSignalName  => "SYNCNeg",
                    RefSignal       => CLK,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_R0_CLK,
                    SetupLow        => tsetup_R0_CLK,
                    HoldHigh        => thold_R0_CLK,
                    HoldLow         => thold_R0_CLK,
                    CheckEnabled    => (PSAVE_nwv ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_SYNC_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_SYNC_CLK );

                VitalSetupHoldCheck (
                    TestSignal      => BLANKIn,
                    TestSignalName  => "BLANKNeg",
                    RefSignal       => CLK,
                    RefSignalName   => "CLK",
                    SetupHigh       => tsetup_R0_CLK,
                    SetupLow        => tsetup_R0_CLK,
                    HoldHigh        => thold_R0_CLK,
                    HoldLow         => thold_R0_CLK,
                    CheckEnabled    => (PSAVE_nwv ='1'),
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & PartID,
                    TimingData      => TD_BLANK_CLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_BLANK_CLK );

                VitalPeriodPulseCheck (
                    TestSignal      =>  CLKIn,
                    TestSignalName  =>  "CLK",
                    Period          =>  tperiod_CLK_posedge,
                    PulseWidthLow   =>  tpw_CLK_negedge,
                    PulseWidthHigh  =>  tpw_CLK_posedge,
                    PeriodData      =>  PD_CLK,
                    XOn             =>  XOn,
                    MsgOn           =>  MsgOn,
                    Violation       =>  Pviol_CLK,
                    HeaderMsg       =>  InstancePath & PartID,
                    CheckEnabled    =>  (PSAVE_nwv ='1') );

                Violation := Pviol_CLK OR Tviol_BLANK_CLK OR Tviol_SYNC_CLK OR
                             Tviol_B_CLK OR Tviol_G_CLK OR Tviol_R_CLK;

            END IF; -- Timing Check Section
            --------------------------------------------------------------------
            -- Functional Section
            --------------------------------------------------------------------
            IF PSAVE_nwv = '1' THEN
                IF rising_edge(CLKIn) THEN
                    Rreg := to_nat(RIn);
                    Greg := to_nat(GIn);
                    Breg := to_nat(BIn);
                    IF SYNC_nwv = '0' THEN
                        IOG_zd := -0.3;
                        IOGNeg_zd := Fior * 1023.0;
                        IOR_zd := 0.0;
                        IORNeg_zd := Fior * 1023.0;
                        IOB_zd := 0.0;
                        IOBNeg_zd := Fior * 1023.0;
                    ELSIF BLANK_nwv = '0' THEN
                        IOG_zd := 0.0;
                        IOGNeg_zd := Fior * 1023.0;
                        IOR_zd := 0.0;
                        IORNeg_zd := Fior * 1023.0;
                        IOB_zd := 0.0;
                        IOBNeg_zd := Fior * 1023.0;
                    ELSE
                        IOR_zd := real(Rreg) * Fior;
                        IORNeg_zd := real(1023 - Rreg) * Fior;
                        IOG_zd := real(Greg) * Fior;
                        IOGNeg_zd := real(1023 - Greg) * Fior;
                        IOB_zd := real(Breg) * Fior;
                        IOBNeg_zd := real(1023 - Breg) * Fior;
                    END IF;
                    IOROut    <= IOR_zd AFTER tpd_CLK_IOR;
                    IORNegOut <= IORNeg_zd AFTER tpd_CLK_IOR;
                    IOGOut    <= IOG_zd + 0.3 AFTER tpd_CLK_IOR;
                    IOGNegOut <= IOGNeg_zd + 0.3 AFTER tpd_CLK_IOR;
                    IOBOut    <= IOB_zd AFTER tpd_CLK_IOR;
                    IOBNegOut <= IOBNeg_zd AFTER tpd_CLK_IOR;
                END IF;
            END IF;

        END PROCESS;

    END BLOCK;
END vhdl_behavioral;