vhdlsourcecodeforadconvertersadv7123.vhd

vhdl源码for模数转换器之七 vhdl源码for模数转换器之七

--------------------------------------------------------------------------------
--  File Name: adv7123.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2003 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    03 Jan 01   Initial release
-- 
--  Output voltages assume a 37.5 Ohm load
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CONVERTER_VHDL
--  Technology: CMOS
--  Part:       ADV7123
-- 
--  Description: Triple 10-Bit Video DAC
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY adv7123 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_R0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_R9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_G9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_B9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_BLANKNeg            : VitalDelayType01 := VitalZeroDelay01;
        tipd_SYNCNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_PSAVENeg            : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_IOR              : VitalDelayType := UnitDelay;
        -- tsetup values: setup times
        tsetup_R0_CLK            : VitalDelayType := UnitDelay;
        -- thold values: hold times
        thold_R0_CLK             : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge          : VitalDelayType := UnitDelay;
        tpw_CLK_negedge          : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLK_posedge : VitalDelayType := UnitDelay;
        -- analog generics
        -- value of Rset resistor in Ohms
        Rset                : real    := 530.0;
        -- value of Vref input In Volts
        Vref                : real    := 1.23;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        R0              : IN    std_ulogic := 'U';
        R1              : IN    std_ulogic := 'U';
        R2              : IN    std_ulogic := 'U';
        R3              : IN    std_ulogic := 'U';
        R4              : IN    std_ulogic := 'U';
        R5              : IN    std_ulogic := 'U';
        R6              : IN    std_ulogic := 'U';
        R7              : IN    std_ulogic := 'U';
        R8              : IN    std_ulogic := 'U';
        R9              : IN    std_ulogic := 'U';
        G0              : IN    std_ulogic := 'U';
        G1              : IN    std_ulogic := 'U';
        G2              : IN    std_ulogic := 'U';
        G3              : IN    std_ulogic := 'U';
        G4              : IN    std_ulogic := 'U';
        G5              : IN    std_ulogic := 'U';
        G6              : IN    std_ulogic := 'U';
        G7              : IN    std_ulogic := 'U';
        G8              : IN    std_ulogic := 'U';
        G9              : IN    std_ulogic := 'U';
        B0              : IN    std_ulogic := 'U';
        B1              : IN    std_ulogic := 'U';
        B2              : IN    std_ulogic := 'U';
        B3              : IN    std_ulogic := 'U';
        B4              : IN    std_ulogic := 'U';
        B5              : IN    std_ulogic := 'U';
        B6              : IN    std_ulogic := 'U';
        B7              : IN    std_ulogic := 'U';
        B8              : IN    std_ulogic := 'U';
        B9              : IN    std_ulogic := 'U';
        BLANKNeg        : IN    std_ulogic := 'U';
        SYNCNeg         : IN    std_ulogic := 'U';
        CLK             : IN    std_ulogic := 'U';
        PSAVENeg        : IN    std_ulogic := 'U';
        IOR             : OUT   real := 0.0;
        IORNeg          : OUT   real := 0.0;
        IOG             : OUT   real := 0.0;
        IOGNeg          : OUT   real := 0.0;
        IOB             : OUT   real := 0.0;
        IOBNeg          : OUT   real := 0.0
    );
--    ATTRIBUTE VITAL_LEVEL0 of adv7123 : ENTITY IS TRUE;
END adv7123;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of adv7123 IS
--    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID            : STRING := "adv7123";
    CONSTANT Fior              : real := 0.2926*Vref/Rset;

    SIGNAL R0_ipd              : std_ulogic := 'U';
    SIGNAL R1_ipd              : std_ulogic := 'U';
    SIGNAL R2_ipd              : std_ulogic := 'U';
    SIGNAL R3_ipd              : std_ulogic := 'U';
    SIGNAL R4_ipd              : std_ulogic := 'U';
    SIGNAL R5_ipd              : std_ulogic := 'U';
    SIGNAL R6_ipd              : std_ulogic := 'U';
    SIGNAL R7_ipd              : std_ulogic := 'U';
    SIGNAL R8_ipd              : std_ulogic := 'U';
    SIGNAL R9_ipd              : std_ulogic := 'U';
    SIGNAL G0_ipd              : std_ulogic := 'U';
    SIGNAL G1_ipd              : std_ulogic := 'U';
    SIGNAL G2_ipd              : std_ulogic := 'U';
    SIGNAL G3_ipd              : std_ulogic := 'U';
    SIGNAL G4_ipd              : std_ulogic := 'U';
    SIGNAL G5_ipd              : std_ulogic := 'U';
    SIGNAL G6_ipd              : std_ulogic := 'U';
    SIGNAL G7_ipd              : std_ulogic := 'U';
    SIGNAL G8_ipd              : std_ulogic := 'U';
    SIGNAL G9_ipd              : std_ulogic := 'U';
    SIGNAL B0_ipd              : std_ulogic := 'U';
    SIGNAL B1_ipd              : std_ulogic := 'U';
    SIGNAL B2_ipd              : std_ulogic := 'U';
    SIGNAL B3_ipd              : std_ulogic := 'U';
    SIGNAL B4_ipd              : std_ulogic := 'U';
    SIGNAL B5_ipd              : std_ulogic := 'U';
    SIGNAL B6_ipd              : std_ulogic := 'U';
    SIGNAL B7_ipd              : std_ulogic := 'U';
    SIGNAL B8_ipd              : std_ulogic := 'U';
    SIGNAL B9_ipd              : std_ulogic := 'U';
    SIGNAL BLANKNeg_ipd        : std_ulogic := 'U';
    SIGNAL SYNCNeg_ipd         : std_ulogic := 'U';
    SIGNAL CLK_ipd             : std_ulogic := 'U';
    SIGNAL PSAVENeg_ipd        : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (R0_ipd, R0, tipd_R0);
        w_2 : VitalWireDelay (R1_ipd, R1, tipd_R1);
        w_3 : VitalWireDelay (R2_ipd, R2, tipd_R2);
        w_4 : VitalWireDelay (R3_ipd, R3, tipd_R3);
        w_5 : VitalWireDelay (R4_ipd, R4, tipd_R4);
        w_6 : VitalWireDelay (R5_ipd, R5, tipd_R5);
        w_7 : VitalWireDelay (R6_ipd, R6, tipd_R6);
        w_8 : VitalWireDelay (R7_ipd, R7, tipd_R7);
        w_9 : VitalWireDelay (R8_ipd, R8, tipd_R8);
        w_10 : VitalWireDelay (R9_ipd, R9, tipd_R9);
        w_11 : VitalWireDelay (G0_ipd, G0, tipd_G0);
        w_12 : VitalWireDelay (G1_ipd, G1, tipd_G1);
        w_13 : VitalWireDelay (G2_ipd, G2, tipd_G2);
        w_14 : VitalWireDelay (G3_ipd, G3, tipd_G3);
        w_15 : VitalWireDelay (G4_ipd, G4, tipd_G4);
        w_16 : VitalWireDelay (G5_ipd, G5, tipd_G5);
        w_17 : VitalWireDelay (G6_ipd, G6, tipd_G6);
        w_18 : VitalWireDelay (G7_ipd, G7, tipd_G7);
        w_19 : VitalWireDelay (G8_ipd, G8, tipd_G8);
        w_20 : VitalWireDelay (G9_ipd, G9, tipd_G9);
        w_21 : VitalWireDelay (B0_ipd, B0, tipd_B0);
        w_22 : VitalWireDelay (B1_ipd, B1, tipd_B1);
        w_23 : VitalWireDelay (B2_ipd, B2, tipd_B2);
        w_24 : VitalWireDelay (B3_ipd, B3, tipd_B3);
        w_25 : VitalWireDelay (B4_ipd, B4, tipd_B4);
        w_26 : VitalWireDelay (B5_ipd, B5, tipd_B5);
        w_27 : VitalWireDelay (B6_ipd, B6, tipd_B6);
        w_28 : VitalWireDelay (B7_ipd, B7, tipd_B7);
        w_29 : VitalWireDelay (B8_ipd, B8, tipd_B8);
        w_30 : VitalWireDelay (B9_ipd, B9, tipd_B9);
        w_31 : VitalWireDelay (BLANKNeg_ipd, BLANKNeg, tipd_BLANKNeg);
        w_32 : VitalWireDelay (SYNCNeg_ipd, SYNCNeg, tipd_SYNCNeg);
        w_33 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_34 : VitalWireDelay (PSAVENeg_ipd, PSAVENeg, tipd_PSAVENeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            RIn       : IN   std_logic_vector(9 downto 0);
            GIn       : IN   std_logic_vector(9 downto 0);
            BIn       : IN   std_logic_vector(9 downto 0);
            BLANKIn   : IN   std_ulogic := 'U';
            SYNCIn    : IN   std_ulogic := 'U';
            CLKIn     : IN   std_ulogic := 'U';
            PSAVEIn   : IN   std_ulogic := 'U';
            VREFIn    : IN   real := 0.0;
            COMPIn    : IN   real := 0.0;
            IOROut    : OUT  real := 0.0;
            IORNegOut : OUT  real := 0.0;