ads7818.vhd

一个关于adc的vhdl源码 一个关于adc的vhdl源码

-------------------------------------------------------------------------------
-- File Name: ads7818.vhd
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Free Model Foundry; http://www.FreeModelFoundry.com
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License version 2 as published by
-- the Free Software Foundation.
--
-- MODIFICATION HISTORY:
-- version: |       author:     |  mod date: | changes made:
--   V1.0     V. Ljubisavljevic    04 Oct 14   Initial release
--
-- Must be compiled with VITAL compliance checking off
-------------------------------------------------------------------------------
-- PART DESCRIPTION:
-- Library:     CONVERTERS_VHDL
-- Technology:  MIXED
-- Part:        ADS7818
--
-- Description: Sampling 12- bit A/D Converter
-------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY ads7818 IS

    GENERIC (
        -- Interconnect path delays
        tipd_CLK            : VitalDelayType01  := VitalZeroDelay01;
        tipd_CSNeg          : VitalDelayType01  := VitalZeroDelay01;
        -- Propagation delays
        tpd_CLK_DOUT        : VitalDelayType01Z := UnitDelay01Z;
        tpd_CSNeg_DOUT      : VitalDelayType01Z := UnitDelay01Z;
        -- Setup/hold violation
        tsetup_CSNeg_CLK    : VitalDelayType    := UnitDelay;
        -- Puls width checks
        tpw_CLK_posedge     : VitalDelayType    := UnitDelay;
        tpw_CLK_negedge     : VitalDelayType    := UnitDelay;
        tpw_CSNeg_posedge   : VitalDelayType    := UnitDelay;
        tpw_CSNeg_negedge   : VitalDelayType    := UnitDelay;
        -- Period checks
        tperiod_CLK_posedge : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING            := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN           := DefaultTimingChecks;
        MsgOn               : BOOLEAN           := DefaultMsgOn;
        XOn                 : BOOLEAN           := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING            := DefaultTimingModel
        );

    PORT (
        CLK   : IN  std_ulogic := 'U';
        CSNeg : IN  std_ulogic := 'U';
        Vref  : IN  real       := 2.5;
        INP   : IN  real       := 0.0;  -- INN
        INN   : IN  real       := 0.0;
        DOUT  : OUT std_ulogic := 'U'
        );

    ATTRIBUTE VITAL_LEVEL0 OF ads7818 : ENTITY IS true;
END ENTITY ads7818;

-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral OF ads7818 IS
    ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS true;

    CONSTANT partID     : STRING                        := "ads7818";
    CONSTANT hiBit      : natural                       := 12;
    SIGNAL   CLK_ipd    : std_ulogic                    := 'U';
    SIGNAL   CSNeg_ipd  : std_ulogic                    := 'U';

    -- mode of operation sample or hold
    SIGNAL   SHMode     : BOOLEAN                       := true;
    -- Sample hold mode
    -- if in sample mode we are longer than Tacq then data is sampled
    SIGNAL   convAlowed : BOOLEAN                       := false;
    SIGNAL   pom_reg    : std_logic_vector((hiBit-1) DOWNTO 0) :=
    (OTHERS => '0');

BEGIN  -- ARCHITECTURE vhdl_behavioral

    convAlowed <= SHmode AFTER 350 ns WHEN SHmode
                  ELSE SHmode;

    ---------------------------------------------------------------------------
    -- Wire delay block
    ---------------------------------------------------------------------------
    WireDelay : BLOCK IS
    BEGIN  -- BLOCK WireDelay
        w1    : VitalWireDelay(CLK_ipd, CLK,tipd_CLK);
        w2    : VitalWireDelay(CSNeg_ipd, CSNeg,tipd_CSNeg);
    END BLOCK WireDelay;

    ---------------------------------------------------------------------------
    -- Behavior Process
    ---------------------------------------------------------------------------
    func : PROCESS (CLK_ipd, CSNeg_ipd)

        CONSTANT maxBitCnt  : natural := 12;    -- Resolution of AD converter

        TYPE mode IS (none, down, up);         -- counter mode
        VARIABLE direction : mode;             -- direction of counting
        VARIABLE ICMode    : BOOLEAN := true;  -- idle or conversion in
                                               -- progress
        VARIABLE PWMode    : BOOLEAN := true;
                                               -- power mode. 1 is
                                               -- for full
                                               -- power and 0 for low
                                               -- power mode

        VARIABLE counter     : natural    := 13;     -- plain counter
        VARIABLE DiffSample  : real       := 0.0;    -- INP - INN
        VARIABLE DZd         : std_ulogic := 'Z';    -- out data zero delayed
        VARIABLE setLSB      : BOOLEAN    := false;  -- if conv hi during conv
        VARIABLE cycleOver   : BOOLEAN    := true;   -- end of operation
        VARIABLE fallingWait : BOOLEAN    := false;

        -- Timing check variables
        VARIABLE Tviol_CSNeg_CLK : X01                 := '0';  -- setup/hold
                                                                --violation flag
        VARIABLE TD_CSNeg_CLK    : VitalTimingDataType;
        VARIABLE PD_CLK          : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_CLK       : X01                 := '0';  -- puls width
                                                                -- violation
        VARIABLE PD_CSNeg        : VitalPeriodDataType := VitalPeriodDataInit;
        VARIABLE Pviol_CSNeg     : X01                 := '0';
        VARIABLE Violation       : X01                 := '0';
        -- Output Glitch Detection Variable
        VARIABLE D_GlitchData    : VitalGlitchDataType;

        PROCEDURE convert (
            sampl           : IN real) IS  -- in sample
            variable tmpref :    real := Vref;
            VARIABLE oldref :    real := 0.0;
            VARIABLE newref :    real := Vref;
        BEGIN  -- PROCEDURE convert
            FOR b IN 0 TO (hiBit-1) LOOP
                IF sampl >= tmpref THEN
                    pom_reg(b) <= '1';
                    IF tmpref >= oldref THEN
                        newref            := tmpref + (tmpref-oldref)/2.0;
                    ELSE
                        newref            := tmpref + (oldref-tmpref)/2.0;
                    END IF;
                    oldref            := tmpref;
                    tmpref            := newref;
                ELSE
                    pom_reg(b) <= '0';
                    IF tmpref >= oldref THEN
                        newref        := tmpref - (tmpref-oldref)/2.0;
                    ELSE
                        newref        := tmpref - (oldref-tmpref)/2.0;
                    END IF;
                    oldref            := tmpref;
                    tmpref            := newref;
                END IF;
            END LOOP;
        END PROCEDURE convert;

        -- purpose: checking voltage levels
        PROCEDURE checkVoltage IS
        BEGIN  -- PROCEDURE checkVoltage
            IF DiffSample > 2.0 * Vref OR DiffSample < 0.0 THEN
                ASSERT false REPORT "Value on differential input is out of"&
                    "range, it could be harmefull for the chip operation"
                    SEVERITY Warning;
            END if;
            IF Vref < 2.0 OR Vref > 2.55 THEN
                ASSERT false
                    REPORT "Reference voltage out of range"
                    SEVERITY WARNING;
            END IF;
            IF INP > 2.0* Vref OR INP < 0.2
                OR INN < (-0.2) OR INN > 0.2 THEN
                ASSERT false
                    REPORT "Voltage range on the input pins is out of the range"
                    & LF & "Result of the coversion is undeterminated"
                    SEVERITY WARNING;
            END IF;

        END PROCEDURE checkVoltage;

    BEGIN  -- PROCESS func

        -----------------------------------------------------------------------
        -- Timing Check Section
        -----------------------------------------------------------------------
        IF TimingChecksOn THEN

            VitalSetupHoldCheck(
                TestSignal     => CSNeg_ipd,
                TestSignalName => "CSNeg",
                RefSignal      => CLK_ipd,
                RefSignalName  => "CLK",
                SetupLow       => tsetup_CSNeg_CLK,
                HoldHigh       => tsetup_CSNeg_CLK,
                CheckEnabled   => true,
                RefTransition  => '\',
                HeaderMsg      => InstancePath & partID,
                TimingData     => TD_CSNeg_CLK,
                XOn            => XOn,
                MsgOn          => MsgOn,
                Violation      => Tviol_CSNeg_CLK
                );

            VitalPeriodPulseCheck(
                TestSignal     => CLK_ipd,
                TestSignalName => "CLK",
                Period         => tperiod_CLK_posedge,
                PulseWidthHigh => tpw_CLK_posedge,
                PulseWidthLow  => tpw_CLK_negedge,
                HeaderMsg      => InstancePath & partID,
                CheckEnabled   => true,
                PeriodData     => PD_CLK,
                XOn            => XOn,
                MsgOn          => MsgOn,
                Violation      => Pviol_CLK
                );

            VitalPeriodPulseCheck(
                TestSignal     => CSNeg_ipd,
                TestSignalName => "CSNeg",
                PulseWidthHigh => tpw_CSNeg_posedge,
                PulseWidthLow  => tpw_CSNeg_negedge,
                HeaderMsg      => InstancePath & partID,
                CheckEnabled   => true,
                PeriodData     => PD_CSNeg,
                XOn            => XOn,
                MsgOn          => MsgOn,
                Violation      => Pviol_CSNeg
                );

            Violation := Tviol_CSNeg_CLK OR Pviol_CSNeg OR Pviol_CLK;

        END IF;

        -----------------------------------------------------------------------
        -- Funcional section
        -----------------------------------------------------------------------
        IF falling_edge(CSNeg_ipd) AND direction = down
            AND counter =  13 AND setLSB THEN
            direction := up;
            PWMode := false;
            ICMode := true;
            setLSB := false;
            SHmode <= false AFTER 5 ns;
        ELSIF falling_edge(CSNeg_ipd) AND counter < 13
        AND NOT convAlowed THEN
            direction := none;
            cycleOver := false;
            PWMode := false;
            DZd := 'Z';
            ICMode := true;
        ELSIF falling_edge(CSNeg_ipd) AND convAlowed THEN
            DiffSample := INP - INN;
            convert(DiffSample);
            SHmode <= false AFTER 5 ns;  -- change to Hold mode
            direction := none;
            checkVoltage;
            fallingWait := true;
        END IF;

        IF rising_edge(CSNeg_ipd) THEN
            IF counter = 13 AND direction = none  THEN
                PWMode := true;
                SHmode <= true AFTER 5 ns;
                setLSB := false;
                DZd := 'Z';
            ELSIF counter < 13 AND direction = down THEN
                setLSB := true;
            ELSIF NOT cycleOver THEN
                cycleOver := true;
                counter := 13;
                PWMode := true;
                SHmode <= true AFTER 5 ns;
                setLSB := false;
            END IF;
        END IF;

        IF falling_edge(CLK_ipd) THEN
            IF direction = none AND to_UX01(CSNeg_ipd) = '0'
                AND cycleOver AND fallingWait THEN
                direction := down;
                DZd := '0';
                ICMode := false;
                counter := 1;
                fallingWait := false;
            ELSIF direction = down AND counter < 13 THEN
                DZd := pom_reg(counter-1);
                counter := counter + 1;
            ELSIF direction = down AND counter = 13 THEN
                DZd := 'Z';
                direction := none;
            ELSIF direction = up AND counter > 2 THEN
                counter := counter - 1;
                DZd := pom_reg(counter-2);
            ELSIF direction = up AND counter = 2 THEN
                IF to_UX01(CSNeg) = '1' THEN
                    DZd := 'Z';
                    SHmode <= true AFTER 5 ns;
                ELSE
                    DZd := '0';
                END IF;
                counter := 13;
                direction := none;
            END IF;
            IF direction = down AND counter = 13 THEN
                IF to_UX01(CSNeg_ipd) = '0' THEN
                    PWMode := false;
                    ICMode := true;
                ELSE
                    SHmode <= true AFTER 5 ns;
                END IF;
            END IF;
        END IF;

        -----------------------------------------------------------------------
        -- Path delay section
        -----------------------------------------------------------------------
        VitalPathDelay01Z(
            OutSignal               => DOUT,
            OutSignalName           => "DOUT",
            OutTemp                 => DZd,
            GlitchData              => D_GlitchData,
            XOn                     => XOn,
            MsgOn                   => MsgOn,
            Paths                   => (
                0 =>
                (InputChangeTime => CLK_ipd'LAST_EVENT,
                PathDelay     => tpd_CLK_DOUT,
                PathCondition => true),
                1 =>
                (InputChangeTime => CSNeg_ipd'LAST_EVENT,
                PathDelay     => tpd_CSNeg_DOUT,
                PathCondition => true)
                )
            );
    END PROCESS func;
END ARCHITECTURE vhdl_behavioral;