timecontrol.tan.qmsg

定时控制电路

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register minute_tens\[0\]~reg0 register minute_ones\[0\]~reg0 264.55 MHz 3.78 ns Internal " "Info: Clock \"clk\" has Internal fmax of 264.55 MHz between source register \"minute_tens\[0\]~reg0\" and destination register \"minute_ones\[0\]~reg0\" (period= 3.78 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.519 ns + Longest register register " "Info: + Longest register to register delay is 3.519 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns minute_tens\[0\]~reg0 1 REG LC_X1_Y15_N9 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y15_N9; Fanout = 7; REG Node = 'minute_tens\[0\]~reg0'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { minute_tens[0]~reg0 } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.239 ns) + CELL(0.590 ns) 1.829 ns always0~22 2 COMB LC_X1_Y14_N4 1 " "Info: 2: + IC(1.239 ns) + CELL(0.590 ns) = 1.829 ns; Loc. = LC_X1_Y14_N4; Fanout = 1; COMB Node = 'always0~22'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.829 ns" { minute_tens[0]~reg0 always0~22 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.212 ns) + CELL(0.478 ns) 3.519 ns minute_ones\[0\]~reg0 3 REG LC_X1_Y15_N3 6 " "Info: 3: + IC(1.212 ns) + CELL(0.478 ns) = 3.519 ns; Loc. = LC_X1_Y15_N3; Fanout = 6; REG Node = 'minute_ones\[0\]~reg0'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.690 ns" { always0~22 minute_ones[0]~reg0 } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.068 ns ( 30.35 % ) " "Info: Total cell delay = 1.068 ns ( 30.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.451 ns ( 69.65 % ) " "Info: Total interconnect delay = 2.451 ns ( 69.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.519 ns" { minute_tens[0]~reg0 always0~22 minute_ones[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.519 ns" { minute_tens[0]~reg0 {} always0~22 {} minute_ones[0]~reg0 {} } { 0.000ns 1.239ns 1.212ns } { 0.000ns 0.590ns 0.478ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns minute_ones\[0\]~reg0 2 REG LC_X1_Y15_N3 6 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y15_N3; Fanout = 6; REG Node = 'minute_ones\[0\]~reg0'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk minute_ones[0]~reg0 } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk minute_ones[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} minute_ones[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns minute_tens\[0\]~reg0 2 REG LC_X1_Y15_N9 7 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y15_N9; Fanout = 7; REG Node = 'minute_tens\[0\]~reg0'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk minute_tens[0]~reg0 } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk minute_tens[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} minute_tens[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk minute_ones[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} minute_ones[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk minute_tens[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} minute_tens[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.519 ns" { minute_tens[0]~reg0 always0~22 minute_ones[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.519 ns" { minute_tens[0]~reg0 {} always0~22 {} minute_ones[0]~reg0 {} } { 0.000ns 1.239ns 1.212ns } { 0.000ns 0.590ns 0.478ns } "" } } { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk minute_ones[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} minute_ones[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk minute_tens[0]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} minute_tens[0]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk hour\[1\] hour\[1\]~reg0 7.102 ns register " "Info: tco from clock \"clk\" to destination pin \"hour\[1\]\" through register \"hour\[1\]~reg0\" is 7.102 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 9 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns hour\[1\]~reg0 2 REG LC_X1_Y15_N8 3 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y15_N8; Fanout = 3; REG Node = 'hour\[1\]~reg0'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk hour[1]~reg0 } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.80 % ) " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns ( 26.20 % ) " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk hour[1]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} hour[1]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.924 ns + Longest register pin " "Info: + Longest register to pin delay is 3.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour\[1\]~reg0 1 REG LC_X1_Y15_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y15_N8; Fanout = 3; REG Node = 'hour\[1\]~reg0'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour[1]~reg0 } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(2.124 ns) 3.924 ns hour\[1\] 2 PIN PIN_41 0 " "Info: 2: + IC(1.800 ns) + CELL(2.124 ns) = 3.924 ns; Loc. = PIN_41; Fanout = 0; PIN Node = 'hour\[1\]'" {  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.924 ns" { hour[1]~reg0 hour[1] } "NODE_NAME" } } { "TimeControl.v" "" { Text "E:/学习资料/2007-2008学年夏季小学期/电子技术课程设计/FPGA/基础实验/TimeControl/TimeControl.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 54.13 % ) " "Info: Total cell delay = 2.124 ns ( 54.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 45.87 % ) " "Info: Total interconnect delay = 1.800 ns ( 45.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.924 ns" { hour[1]~reg0 hour[1] } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.924 ns" { hour[1]~reg0 {} hour[1] {} } { 0.000ns 1.800ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.954 ns" { clk hour[1]~reg0 } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "2.954 ns" { clk {} clk~out0 {} hour[1]~reg0 {} } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.924 ns" { hour[1]~reg0 hour[1] } "NODE_NAME" } } { "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus7.2/quartus/bin/Technology_Viewer.qrui" "3.924 ns" { hour[1]~reg0 {} hour[1] {} } { 0.000ns 1.800ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 09 22:43:55 2008 " "Info: Processing ended: Wed Jul 09 22:43:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}